AD9213 datasheet(2/110 Pages) AD

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AD9213

Data Sheet

Rev. A | Page 2 of 110

TABLE OF CONTENTS

Features .............................................................................................. 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 7

Timing Specifications .................................................................. 8

Absolute Maximum Ratings.......................................................... 10

Thermal Characteristics ............................................................ 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Typical Performance Characteristics ........................................... 14

AD9213-6G ................................................................................. 14

AD9213-10G............................................................................... 20

Equivalent Circuits......................................................................... 27

Theory of Operation ...................................................................... 30

ADC Architecture ...................................................................... 30

Analog Input Considerations.................................................... 30

Voltage Reference ....................................................................... 31

Clock Input Considerations...................................................... 32

TMU................................................................................................. 33

ADC Overrange and Fast Detect.................................................. 34

ADC Overrange.......................................................................... 34

Fast Threshold Detection (FD)................................................. 34

Digital Downconverter (DDC)..................................................... 35

DDC General Description ........................................................ 35

DDC Frequency Translation..................................................... 37

DDC Decimation Filters............................................................ 44

DDC Gain Stage ......................................................................... 48

DDC Complex to Real Conversion.......................................... 48

DDC Example Configurations ................................................. 49

Signal Monitor ................................................................................ 53

SPORT Over JESD204B............................................................. 53

Digital Outputs ............................................................................... 56

Introduction to the JESD204B Interface ................................. 56

JESD204B Overview .................................................................. 56

Functional Overview ................................................................. 57

JESD204B Link Establishment ................................................. 57

Physical Layer (Driver) Outputs .............................................. 59

Setting Up the AD9213 Digital Interface................................ 60

Latency............................................................................................. 63

End to End Total Latency.......................................................... 63

Example Latency Calculations.................................................. 63

LMFC Referenced Latency........................................................ 63

Deterministic Latency.................................................................... 65

Subclass 0 Operation.................................................................. 65

Subclass 1 Operation.................................................................. 65

Multichip Synchronization (MCS)............................................... 67

Averaged SYSREF Mode For MCS........................................... 67

Sampled SYSREF Mode............................................................. 67

MCS Averaged SYSREF Mode Setup....................................... 68

Test Modes....................................................................................... 70

JESD204B Test Modes ............................................................... 70

Data Link Layer Test Modes ..................................................... 70

Serial Port Interface (SPI).............................................................. 73

Configuration Using the SPI..................................................... 73

SPI Accessible Features.............................................................. 73

Hardware Interface..................................................................... 73

Memory Map .................................................................................. 74

Reading the Memory Map Register Tables............................. 74

Applications Information ............................................................ 108

Startup Sequence ...................................................................... 108

Changing Sample Clock Frequency Without Power Down108

Power Supply Recommendations........................................... 109

Outline Dimensions..................................................................... 110

Ordering Guide ........................................................................ 110

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