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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9213 датащи(PDF) 49 Page - Analog Devices |
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AD9213 датащи(HTML) 49 Page - Analog Devices |
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49 / 110 page  Data Sheet AD9213 Rev. A | Page 49 of 110 Figure 109 shows a simplified block diagram of the complex to real conversion. LOW-PASS FILTER 2 I Q REAL HB1 FIR LOW-PASS FILTER 2 HB1 FIR 0 1 COMPLEX TO REAL ENABLE Q 90° 0° + – COMPLEX TO REAL CONVERSION I Q I Q GAIN STAGE cos(wt) sin(wt) I/REAL 0dB OR 6dB 0dB OR 6dB 0dB OR 6dB 0dB OR 6dB fS/4 Figure 109. Complex to Real Conversion Block DDC EXAMPLE CONFIGURATIONS Table 22 and Table 23 describes the register settings for multiple DDC example configurations, where bandwidths are with <−0.001 dB of pass-band ripple and >100 dB of stop band alias rejection. Table 22. Example DDC Configurations per ADC Channel Pair, Full Bandwidth Mode Chip Application Layer Chip Decimation Ratio (DCM) DDC Output Type Bandwidth Per DDC1 No. of Virtual Converters Required Register Settings Full Bandwidth Mode 1 Don’t care 50% × fS 1 0x606 = 0x00 (full bandwidth mode) 0x607 = 0x00 (chip decimate by 1) 0x630 = 0x00 (don’t care) 0x631 = 0x00 (don’t care) 1 fS is the ADC sample rate. |
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