LT4239 datasheet(17/24 Pages) AD

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LT4239

Rev. 0

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Thus, the maximum power dissipated in the MOSFET M1

during active current limiting is 5.6A • 12V = 67.2W for

100µs. The SOA curve of the PSMN6R1-30YLD shows

500W (50A at 10V) for 100µs, satisfying this requirement.

The start-up timer capacitor (CST) determines the total

time allowed for a successful startup from the completion

of the debounce to the start of the PG timer. For the STMR

ramp-up time of 200ms which is 2 times longer than the

time before the PG timer starts (Equation 9).

CST = 200ms • 0.008[µF⁄ms]≅ 1.6µF

(9)

Since the MOSFET M2 turns on only after the load capaci-

tor is fully charged through M1, the MOSFET is selected to

handle the power dissipation during active current limiting

for 100µs.

Use Equation 10 to calculate the maximum short-circuit

current using the maximum active current limit threshold,

∆VSENSE2(ACL)(MAX) and minimum RS2 value where there

are 12 parallel 1mΩ sense resistors for RS2.

ISHORT2(MAX) =

∆VSENSE2(ACL)(MAX)

RS2(MIN) ⁄ 12

17mV

0.99mΩ⁄ 12

= 206A

(10)

If the output is shorted to a voltage below 3.7V, the MOSFET

M2 will be turned off instantly without active current limit-

ing and the fault is latched-off. Thus, the maximum power

dissipated in the MOSFET during active current limiting

if the 12V output collapsed to 4V is 206A • (12V – 4V) =

1648W for 100µs. Though the MOSFETs operate in par-

allel during active current limiting, they only provide the

SOA of a single MOSFET due to offset mismatch between

the gate thresholds. The MOSFET with the lowest thresh-

old may carry more current than the others and as it gets

hotter, it carries even more current since threshold voltage

has a negative temperature coefficient. The SOA curve of

the PSMN1R0-25YLD shows 2500W (250A at 10V) for

100µs, satisfying this requirement.

Another selection criterion is to use a smaller RDS(ON) of

1mΩ or less for the MOSFET to minimize the voltage drop

keeping the power dissipation within limits at maximum

load current. In the design, eight MOSFETs in parallel are

used to reduce the dissipated power in each MOSFET. The

effective RDS(ON) is kept low enough to avoid triggering

the FET-Bad fault threshold.

The fault timer capacitor (CFT) at CBTMR pin is used

to prevent power dissipation in the MOSFET M2 from

exceeding its SOA rating during an overcurrent fault. Use

Equation 11 to calculate the worst-case short-circuit cur-

rent during the fault timer period before active current

limiting is activated.

ISHORT2(WORST) =

∆VSENSE2(ACL)(MAX) – ∆VSENSE2(CB)(MIN)

RS2(MIN) ⁄ 12

ISHORT2(WORST) =

17mV

− 9.5mV

0.99mΩ⁄ 12

= 91A

(11)

Assuming the short-circuit current is divided equally

amongst the eight parallel MOSFETs, the maximum power

dissipated in each MOSFET during the fault timer period if

the 12V output collapsed to 4V is (91A/8) • (12V – 4V) =

91W. The SOA curve of the PSMN1R0-25YLD shows

200W (20A at 10V) for 10ms.

The MOSFET’s SOA rating requirement is satisfied for a

fault timer period of 5ms (Equation 12).

CFT = 5ms • 0.008[µF⁄ms] ≅ 47nF

(12)

Finally, select the values for the resistive voltage divider

at the UV pin that defines the undervoltage threshold of

9.7V for the 12V supply. Since the leakage current for the

UV pin can be as high as ±1µA, the total resistance in the

divider should be low enough to minimize the resulting

offset error. Calculate the bottom resistor R1 based on

Equation 13 to obtain less than ±0.2% error due to leak-

age current.

VUV(TH)

I(LEAK)

⎛

⎝

⎜

⎞

⎠

⎟ • 0.2% =

1.232V

1µA

⎛

⎝⎜

⎞

⎠⎟

• 0.2%

= 2.4k (13)

Choose R1 to be 2kΩ to achieve less than ±0.2% error and

then solving Equation 14 for R2, results in R2 = 13.7kΩ.

VIN(UV)

VUV(TH)

− 1

⎛

⎝

⎜

⎞

⎠

⎟ •R1

9.7V

1.232V

− 1

⎛

⎝⎜

⎞

⎠⎟

• 2k

= 13.7k

(14)

A 0.1µF capacitor C2 is placed on the UV pin to prevent

supply glitches from turning off the MOSFETs.

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