LT4239 datasheet(13/24 Pages) AD

13 / 24 page

LT4239

Rev. 0

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amplifier regulates the gate of the MOSFET to maintain

the ACL threshold across the sense resistor. At this point,

an internal fault timer runs for 100µs until it times out.

The MOSFET is turned off with GATE2 pulled to OUT by

50mA, and the FLT pin also pulls low.

In the event of a severe short-circuit fault on the 12V

output after power good, the output current can rapidly

surge. If the fast comparator threshold ∆VSENSE2(FAST)

(40mV) is exceeded, the LT4239 responds within 1µs to

bring the current under control by pulling GATE2 to OUT

without latching off the fault. If the OUT voltage falls below

3.7V, GATE2 will also be pulled down to OUT quickly to

turn off the MOSFET and the fault is latched-off with the

FLT pin pulling low. All the overcurrent faults will activate

the cool-off cycle for the MOSFETs to cool down before

the output can be restarted.

The waveforms in Figure 3 show how the output turns off

following an overcurrent fault after power good.

2ms/DIV

CBTMR

1V/DIV

4239 F03

∆VGATE2

10V/DIV

ILOAD

100A/DIV

VOUT

10V/DIV

Figure 3. Overcurrent Fault After Power Good

Undervoltage Fault

The UV pin functions as a turn-on control and input sup-

ply monitor. A resistive divider connected between the

supply input and GND at the UV pin monitors the supply

for an undervoltage condition. The undervoltage thresh-

old is set by proper selection of the resistors at the UV

rising threshold voltage (1.232V). For Figure 1, if R1 = 2k,

R2 = 13.7k, the input supply undervoltage threshold is

set to 9.7V.

An undervoltage fault occurs if the input supply falls

below its undervoltage threshold. If the UV pin voltage

falls below 1.182V for longer than 270µs but remains

above 0.6V, the MOSFETs are turned off by a 10mA

pull-down current from both GATE1 and GATE2 to OUT.

However, if the UV pin voltage drops below 0.6V, it turns

off the MOSFETs and clears the fault latch. The GATE1

can start up again only after a debounce delay when the

input supply is restored above its undervoltage threshold.

During the undervoltage fault condition, FLT will not be

pulled low, but PG will be pulled low as both GATE pins

are pulled low.

FET-Bad Fault

In a Hot Swap application, several possible faults can

prevent the MOSFETs from turning on and reaching a low

impedance state. A damaged MOSFET may have leakage

from gate to drain or have degraded RDS(ON). Debris on

the board may also produce leakage or a short-circuit from

the MOSFET’s gate to the source, the drain, or to ground.

Under these conditions, the LT4239 may not be able

to pull the GATE pins high enough to fully enhance the

MOSFETs. If GATE1 or GATE2 voltage fail to reach their

10V thresholds above OUT when the STMR voltage

reaches its 1.232V threshold, a start-up fault condition is

generated. FLT pin will be pulled low, and the GATE pins

are pulled down to OUT with a 10mA current source. A

start-up fault will not activate the 512 timing cycles at

CBTMR pin for MOSFET cool-off.

If FET-Bad conditions occur after the load is turned on, the

MOSFET M2 may not reach the intended RDS(ON) when the

GATE2 drive is fully enhanced. This can put the MOSFET

in a condition where the power in the MOSFET is higher

than its continuous power capability, even though the

current is below the current limit. The LT4239 monitors

the integrity of the MOSFET M2 in two ways, and acts on

them in the same manner.

First, the LT4239 monitors the voltage between the

MOSFET’s drain and the OUTK pin that include the sense

resistor drop. A bad M2 MOSFET’s Drain-to-Source

voltage is detected if the voltage is greater than the 100mV

FET-Bad fault threshold.

Second, the LT4239 monitors the GATE2 voltage. A dam-

aged MOSFET may cause the GATE2 voltage to fall due to

a resistive short from the gate to either the source or drain

APPLICATIONS INFORMATION

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