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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM8S007C8 датащи(PDF) 47 Page - STMicroelectronics |
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STM8S007C8 датащи(HTML) 47 Page - STMicroelectronics |
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47 / 93 page  DS8633 Rev 6 47/93 STM8S007C8 Electrical characteristics 82 Figure 8. fCPUmax versus VDD Table 17. Operating conditions at power-up/power-down Symbol Parameter Conditions Min Typ Max Unit tVDD VDD rise time rate - 2(1) 1. Guaranteed by design. - ∞ µs/V VDD fall time rate - 2(1) - ∞ tTEMP Reset release delay VDD rising - - 1.7(1) ms VIT+ Power-on reset threshold(2) 2. If VDD is below 2.95 V, the code execution is guaranteed above the VIT- and VIT+ thresholds. RAM content is kept. The EEPROM programming sequence must not be initiated. - 2.65 2.8 2.95 V VIT- Brown-out reset threshold - 2.58 2.73 2.88 V VHYS(BOR) Brown-out reset hysteresis -- 70 - mV fCP U [MHz] Supply voltage [ V] 24 12 8 4 0 2.95 4.0 5.0 16 5. 5 Functionality not guaranteed in this area Functionality guaranteed with 0 wait state Functionality guaranteed with 1 wait state MS19413V1 |
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