STM8L151X6 datasheet(63/147 Pages) STMICROELECTRONICS

63 / 147 page

DS6948 Rev 11

63/147

STM8L151x6/8 STM8L152x6/8

Interrupt vector mapping

TIM2/

USART2

Capture/Compare/USART

2 interrupt

Yes

Yes(3)

0x00 8058

TIM3/

USART3

TIM3 Update

/Overflow/Trigger/Break/

USART3 transmission

complete/transmit data

interrupt

Yes

Yes(3)

0x00 805C

TIM3/

USART3

TIM3 Capture/Compare/

USART3 Receive register

data full/overrun/idle line

detected/parity error/

interrupt

Yes

Yes(3)

0x00 8060

TIM1

Update /overflow/trigger/

COM

Yes(3)

0x00 8064

TIM1

Capture/Compare

Yes(3)

0x00 8068

TIM4

Update/overflow/trigger

Yes

Yes(3)

0x00 806C

SPI1

End of Transfer

Yes

Yes(3)

0x00 8070

USART 1/

TIM5

USART1 transmission

complete/transmit data

TIM5 update/overflow/

trigger/break

Yes

Yes(3)

0x00 8074

USART 1/

TIM5

USART1 Receive register

data full/overrun/idle line

detected/parity error/

TIM5 capture/compare

Yes

Yes(3)

0x00 8078

I2C1/SPI2

I2C1 interrupt(5)/

SPI2

Yes

Yes(3)

0x00 807C

1. The Low-power wait mode is entered when executing a WFE instruction in Low-power run mode.

2. The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts.

3. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes

back to WFE mode. When this interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.

4. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port

E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031).

5. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.

Table 11. Interrupt mapping (continued)

IRQ

No.

Source

block

Description

Wakeup

from Halt

mode

Wakeup

from

Active-halt

mode

Wakeup

from Wait

(WFI

mode)

Wakeup

from Wait

(WFE

mode)(1)

Vector

address

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