MIC2182 datasheet(30/40 Pages) MICROCHIP

30 / 40 page

MIC2182

DS20006644A-page 30

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2022 Microchip Technology Inc. and its subsidiaries

5.11 PCB Layout and Checklist

PCB layout is critical to achieve reliable, stable and

efficient performance. A ground plane is required to

control EMI and minimize the inductance in power and

signal return paths.

The following guidelines should be followed to insure

proper operation of the circuit.

• Signal and power grounds should be kept

separate and connected at only one location.

Large currents or high di/dt signals that occur

when the MOSFETs turn on and off must be kept

away from the small signal connections.

• The connection between the current-sense

resistor and the MIC2182 current-sense inputs

(Pins 8 and 9) should have separate traces,

routed from the terminals directly to the IC pins.

The traces should be routed as closely as

possible to each other and their length should be

minimized. Avoid running the traces under the

inductor and other switching components. A 1 nF

to 0.1 µF capacitor placed between Pins 8 and 9

will help attenuate switching noise on the current

sense traces. This capacitor should be placed

close to Pins 8 and 9.

• When the high-side MOSFET is switched on, the

critical flow of current is from the input capacitor

through the MOSFET, inductor, sense resistor,

output capacitor, and back to the input capacitor.

These paths must be made with short, wide

pieces of trace. It is good practice to locate the

ground terminals of the input and output

capacitors close to each other.

• When the low-side MOSFET is switched on,

current flows through the inductor, sense resistor,

output capacitor, and MOSFET. The source of the

low-side MOSFET should be located close to the

output capacitor.

• The freewheeling diode, D1 in the Block

Diagrams, conducts current during the dead time,

when both MOSFETs are off. The anode of the

diode should be located close to the output

capacitor ground terminal and the cathode should

be located close to the input side of the inductor.

• The 4.7 µF capacitor, which connects to the VDD

terminal (Pin 11) must be located right at the IC.

The VDD terminal is very noise sensitive and

placement of this capacitor is very critical.

Connections must be made with wide trace. The

capacitor may be located on the bottom layer of

the board and connected to the IC with multiple

vias.

• The VIN bypass capacitor should be located close

to the IC and connected between Pins 10 and 12.

Connections should be made with a ground and

power plane or with short, wide trace.

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