MIC2182 datasheet(18/40 Pages) MICROCHIP

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MIC2182

DS20006644A-page 18



2022 Microchip Technology Inc. and its subsidiaries

floats high while continuing to keep the high-side

MOSFET on. When the low-side switch is turned back

on, CBST is recharged through D2.

The drive voltage is derived from the internal 5V VDD

bias supply. The nominal low-side gate drive voltage is

5V and the nominal high-side gate drive voltage is

approximately 4.5V due the voltage drop across D2. A

fixed 80 ns delay between the high-side and low-side

driver transitions is used to prevent current from

simultaneously flowing unimpeded through both

MOSFETs.

4.5

Oscillator and Sync

The internal oscillator is free running and requires no

external components. The nominal oscillator frequency

is 300 kHz. If the output voltage is below approximately

0.95V, the oscillator operates in a frequency-foldback

mode and the switching frequency is reduced to

60 kHz.

The SYNC input (Pin 5) allows the MIC2182 to

synchronize with an external clock signal. The rising

edge of the sync signal generates a reset signal in the

oscillator, which turns off the low-side gate drive output.

The high-side drive then turns on, restarting the

switching cycle. The sync signal is inhibited when the

controller operates in skip mode or during frequency

foldback. The sync signal frequency must be greater

than the maximum specified free running frequency of

the MIC2182. If the synchronizing frequency is lower,

double pulsing of the gate drive outputs will occur.

When not used, the sync pin must be connected to

ground.

Figure 4-8 shows the timing between the external sync

signal (trace 2), the low-side drive (trace 1) and the

high-side drive (trace R1). There is a delay of

approximately 250 ns between the rising edge of the

external sync signal and turnoff of the low-side

MOSFET gate drive.

Some concerns of operating at higher frequencies are:

• Higher power dissipation in the internal VDD

regulator. This occurs because the MOSFET

gates require charge to turn on the device. The

average current required by the MOSFET gate

increases with switching frequency. This

increases the power dissipated by the internal

VDD regulator. Figure 4-9 and Figure 4-10 shows

the total gate charge which can be driven by the

MIC2182 over the input voltage range, for

different values of switching frequency. The total

gate charge includes both the high-side and

low-side MOSFETs. The larger SOIC package is

capable of dissipating more power than the SSOP

package and can drive larger MOSFETs with

higher gate drive requirements.

FIGURE 4-8:

Sync Waveforms.

• Reduced maximum duty cycle due to switching

transition times and constant delay times in the

controller. As the switching frequency increased,

the switching period decreases. The switching

transition times and constant delays in the

MIC2182 start to become noticeable. The effect is

to reduce the maximum duty cycle of the

controller. This will cause the minimum input to

output differential voltage (dropout voltage) to

increase.

FIGURE 4-9:

SOIC Package Device

MOSFET Gate Charge Driving Ability vs. Input

Voltage.

FIGURE 4-10:

SSOP Package Device

MOSFET Gate Charge Driving Ability vs. Input

Voltage.

TIME

100

1216 2024 2832

SUPPLY VOLTAGE (V)

400kHz

300kHz

500kHz

SOIC

100

1216 2024 2832

SUPPLY VOLTAGE (V)

SSOP

400kHz

300kHz

500kHz

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