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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32F469AE датащи(PDF) 23 Page - STMicroelectronics |
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STM32F469AE датащи(HTML) 23 Page - STMicroelectronics |
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23 / 220 page  DS11189 Rev 7 23/220 STM32F469xx Functional overview 47 Figure 6. STM32F469xx Multi-AHB matrix 2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. ARM Cortex-M4 GP DMA1 GP DMA2 MAC Ethernet USB OTG HS Bus matrix-S ICODE DCODE Flash memory SRAM1 160 Kbyte SRAM2 32 Kbyte AHB2 peripherals AHB1 peripherals FMC external MemCtl MS33862V1 CCM data RAM 64-Kbyte APB1 APB2 SRAM3 128 Kbyte LCD-TFT Chrom ART Accelerator(DMA2D) QuadSPI |
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