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18

DS-DMX250 R 0.80

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5.

DMX250 Registers

The DMX250 contains internal registers for configuration and status checks. Each of these registers is accessible by

the DMX-controller for Read and Write operations. The access to these registers is different for each interface

protocol and described in the protocol interfaces sections. This section elaborates on the registers and their

default values after power-up/reset.

Table 11 - Registers summary table

Register name

Addr.

Description

REG_1 - 'Device Control 1'

0x01

Transmit level control

REG_2 - 'Frequency Select'

0x02

Carrier frequency selection

Reg_3 - 'Sleep Control'

0x03

Sleep modes control

REG_59 – DMX250 UUID[47:40]

0x59

Read only - UUID[47:40]

REG_5A - DMX250 UUID[39:32]

0x5A

Read only - UUID[39:32]

REG_5B - DMX250 UUID[31:24]

0x5B

Read only - UUID[31:24]

REG_5C - DMX250 UUID[23:16]

0x5C

Read only - UUID[23:16]

REG_5D - DMX250 UUID[15:8]

0x5D

Read only - UUID[15:8]

REG_5E - DMX250 UUID[7:0]

0x5E

Read only - UUID[7:0]

5.1

REG_1 - 'Device Control 1' (Address 0x01)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

[1]

[1]

[1]

[1]

R/W [1]

[0]

[0]

R/W [0]

1

1

1

1

TX signal level

0

0

Enable TXO

high power

Bit [0]

- Enable TXO high power. Set this bit to enable maximal TXO drive of 66mA, clear this bit for maximal

TXO drive of 33mA (see section ‎2.5.6).

Bit [1]

- '0'

Bit [2]

- '0'

Bit [3]

- TX signal level control at TXO pin: '0' = 1Vpp, '1'- 2Vpp (see section ‎2.5.6).

Bit [7:4]

- '1111'

R - Readable bit,

W - Writeable bit

[x] - Value on power-up. ‘1’ - bit is set; ‘0’ - bit is cleared

5.2

REG_2 - 'Frequency Select' (Address 0x02)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R/W [0]

R/W [1]

R/W [0]

R/W [1]

R/W [0]

R/W [0]

R/W [0]

R/W [0]

Carrier Frequency Configuration

Bits [7:0]

- Carrier Frequency configuration from in-band. Default configuration is 13MHz

(See section ‎3.4 - Carrier frequency ).

5.3

REG_3 - 'Sleep Control (Address 0x03)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

W [0]

[0]

[0]

[0]

R/W [1]

R/W [1]

R/W [0]

R/W [0]

Enter Sleep

mode

0

0

0

Auto WUM

Long WUM

Sleep modes

selection

Bit [1:0]

- '00' - Enhanced Sleep mode [SLP1], '01' -Fast wake-up Sleep mode[SLP2], '10' - Low-power sleep

mode [SLP3], '11' - Deep Sleep mode [SLP4] (see section ‎4.3).

Bit [2]

- Control powerline wake-up message duration (see Table 10).

Bit [3]

-Auto wake-up message (WUM): ‘0’ disables transmission of WUM after wakeup from NSLEEP pin.

Bits [6:4]

- '0'

Bit [7]

- Enter Sleep mode reg. Instead of entering Sleep mode through the NSLEEP pin, the user can activate

the Sleep mode selected in bits [1:0], by setting bit[7]. After entering Sleep mode, bit [7] is

automatically cleared to '0'.

R - Readable bit,

W - Writeable bit

[x] - Value on power-up. ‘1’ - bit is set; ‘0’ - bit is cleared