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AS3715 датащи(PDF) 77 Page - ams AG

номер детали AS3715
подробное описание детали  Dual Power Path PMIC
PDF  160 Pages
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производитель  AMSCO [ams AG]
домашняя страница  http://www.ams.com
Logo AMSCO - ams AG

AS3715 датащи(HTML) 77 Page - ams AG

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ams Datasheet, Confidential
Page 77
[v1-00] 2014-Sep-10
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AS3715 − Detailed Description – System Functions
In order to change the data direction a repeated START
condition is issued on the 1st SCL pulse after the acknowledge
bit of the word address transfer. After the reception of the
device-read address, the slave becomes the transmitter. In this
state the slave transmits register data located by the previous
received word address vector. The master responds to the data
byte with a not-acknowledge, and issues a STOP condition on
the bus.
Figure 80:
I²C Sequential Read
I²C Sequential Read: Shows the format of an I²C sequential read access.
Sequential Read is the extended form of Random Read, as more
than one register-data bytes are transferred subsequently. In
difference to the Random Read, for a sequential read the
transferred register-data bytes are responded by an
acknowledge from the master. The number of data bytes
transferred in one sequence is unlimited (consider the behavior
of the word-address counter). To terminate the transmission the
master has to send a not-acknowledge following the last data
byte and generate the STOP condition subsequently.
Figure 81:
I²C Current Address Read
I²C Current Address Read: Shows the format of an I²C current address read access.
To keep the access time as small as possible, this format allows
a read access without the word address transfer in advance to
the data transfer. The bus is idle and the master issues a START
condition followed by the Device-Read address. Analogous to
Random Read, a single byte transfer is terminated with a
not-acknowledge after the 1st register byte. Analogous to
Sequential Read an unlimited number of data bytes can be
transferred, where the data bytes has to be responded with an
acknowledge from the master. For termination of the
transmission the master sends a not-acknowledge following
the last data byte and a subsequent STOP condition.
A
DW
S
WA
A Sr
DR
A data 1 A data 2 A
...
data n
RA++
RA++
RA++
P
N
S
DR
A data 1 A data 2 A
...
data n
RA++
RA++
RA++
P
N



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