AS3715 datasheet(71/160 Pages) AMSCO

71 / 160 page

ams Datasheet, Confidential

Page 71

[v1-00] 2014-Sep-10

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AS3715 − Detailed Description – System Functions

Watchdog

Description

The purpose of the watchdog is to detect a deadlock of the

software. If the watchdog is active, it must receive a continuous

trigger signal within a programmable time window. If there is

no signal anymore for a certain time period from a defined pad

or special serial interface bit, it starts either a complete reset

cycle or initiates the power OFF sequence.

The watchdog is highly configurable by the following register

bits:

• The complete block can be switched ON by wtdg_on = 1

and OFF by wtdg_on = 0.

• The watchdog time window is defined by the register

wtdg_timer between 1s and 128s.

• The trigger signal can be either triggered by setting

wtdg_sw_sig or using a HW signal on one of the GPIO pins

(gpioX_iosf=9).

• If the watchdog expires, the system can start

automatically a reset cycle if wtdg_reset_on = 1 and

wtdg_pweroff = 0, or perform a power down if

wtdg_reset_on = 1 and wtdg_pweroff = 1.

•If wtdg_reset_on = 0 and wtdg_pweroff = 0 only an

interrupt is generated (if the interrupt is enabled)

• Whether the watchdog caused a reset can be seen in the

reset_reason.

Interrupt Generation

Description

The interrupt controller generates an interrupt request for the

host controller as soon as one or more of the bits in the Interrupt

1…3 register are set by pulling high pin INT (INT has to be

selected as GPIO output function). The output polarity can be

changed to active low (XINT ) by using the gpioX_invert bit of

the selected GPIO. All the interrupt sources can be enabled in

the Interrupt Mask 1…3 register. The Interrupt 1…3 registers

are cleared automatically after the host controller has read

them. To prevent the AS3715 device from losing an interrupt

event, the register that is read is captured before it is

transmitted to the host controller via the serial interface. As

soon as the transmission of the captured value is complete a

logical AND operation with the bit wise inverted captured value

is applied to the register to clear all interrupt bits that have

already been transmitted. Clearing the read interrupt bits takes

2 clock cycles, a read access to the same register before the

clearing process has completed will yield a value of ‘0’. Note that

an interrupt that has been present at the previous read access

will be cleared as well in case it occurs again before the clearing

process has completed.

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