FS8160 datasheet(7/13 Pages) ETC1

7 / 13 page

FS8160

Page 7

April 2003

Phase/Frequency Detector (PFD)

The PFD compares an internal input frequency divider output signal, f

V, with an internal

reference frequency divider output signal, f

R, and generates an error signal which is pro-

portional to the phase error between f

V and fR. The polarity of the PFD is user-selectable

using serial input data control bits (see Table 5 on page 9). The input/output waveforms

for a positive polarity PFD (VCO frequency increases with increasing tuning voltage) are

shown in Fig. 1.

Fig. 1 – Positive polarity PFD input/output waveforms

Charge Pump

The charge pump output sources/sinks current to/from an external loop filter, which con-

verts the charge into a voltage used to control the external VCO’s frequency. When the

PLL is locked, the charge pump output is primarily in a high impedance (high-Z) state.

The magnitude of the charge pump output current is user-selectable using serial input data

control bits (see Table 5 on page 9).

Serial Input Data Format

The divide ratios for the input (N) and reference (R) dividers are input using an 18-bit

serial interface consisting of separate clock (CLK), data (DATA), and latch enable (LE)

lines. The format of the serial data is shown in Fig. 2.

Fig. 2 – Serial input data format

The data on the DATA line is written to the shift register on the rising edge of the CLK

signal and is input with MSB first. The data on the DATA line should be changed on the

falling edge of CLK, and LE should be held low while data is being written to the shift

latches when LE is set high depending upon the state of the control bits (CB[1:0]) as indi-

high-Z

DOM, DOA

DATA[15:0]

CB[1:0]

FS8160 датащи(PDF) 7 Page - List of Unclassifed Manufacturers