FS8160 datasheet(6/13 Pages) ETC1

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FS8160

Page 6

April 2003

Functional Description

The FS8160 dual phase-locked loop (PLL) IC contains two identical PLLs (main and aux-

iliary). Both the main and auxiliary PLLs share the crystal oscillator, serial data input

logic, and multi-function lock detector output circuits. Each PLL has its own program-

mable input and reference frequency dividers, phase/frequency detectors, programmable

charge pumps, and digital-filtered lock detectors.

Programmable Input Frequency Divider

The VCO input to the FIN pin is divided by the programmable divider and then internally

output to the phase/frequency detector (PFD) as f

V. The programmable input frequency

divider consists of a ÷ 16/17 (P/P+1) dual-modulus prescaler and a 16-bit (N) counter,

which is further comprised of a 4-bit swallow (A) counter, and a 12-bit main (B) counter.

The total divide ratio, M, is related to values for P, A, and B through the relation

with

The minimum programmable divisor for continuous counting is given by

and the valid total divide ratio range for the input

divider is

Programmable Reference Frequency Divider

The crystal oscillator output is divided by the programmable divider and then internally

output to the PFD as f

R. The programmable reference frequency divider consists of a 13-

bit reference (R) counter. Because of its design, the valid total divide ratio range for the

reference divider is

() AP

B A

–

()

B A.

≥

PP 1

–

()

240,

240 to 65535.

2 to 4095.

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