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UCD7100APWPR датащи(PDF) 12 Page - Texas Instruments |
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UCD7100APWPR датащи(HTML) 12 Page - Texas Instruments |
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12 / 30 page ![]() When the CS voltage is below ILIM, the driver output will follow the PWM input. The CLF digital output flag can be monitored by the host controller to determine when a current limit event occurs and to then apply the appropriate algorithm to obtain the desired current limit profile. One of the main benefits of this local protection feature is that the UCD7K devices can protect the power stage if the software code in the digital controller becomes corrupted and hangs up. If the controller’s PWM output stays high, the local current sense circuit will turn off the driver output when an over-current condition occurs. The system would likely go into a retry mode because; most DSP and microcontrollers have on-board watchdog, brown-out, and other supervisory peripherals to restart the device in the event that it is not operating properly. But these peripherals typically do not react fast enough to save the power stage. The UCD7K’s local current limit comparator provides the required fast protection for the power stage. The CS threshold is 25 mV below the ILIM voltage. This way, if the user attempts to command zero current (ILIM < 25 mV) while the CS pin is at ground, for example at start-up, the CLF flag latches high until the IN pin receives a pulse. At start-up it is necessary to ensure that the ILIM pin always greater than the CS pin for the handshaking to work as described below. If for any reason the CS pin comes to within 25 mV of the ILIM pin during start-up, then the CLF flag is latched high and the digital controller must poll the UCD7K device, by sending it a narrow IN pulse. If the fault condition is not present the IN pulse resets the CLF signal to low indicating that the UCD7K device is ready to process power pulses. 9.3.3 Handshaking The UCD7K family of devices have a built-in handshaking feature to facilitate efficient start-up of the digitally controlled power supply. At start-up the CLF flag is held high until all the internal and external supply voltages of the UCD7K device are within their operating range. Once the supply voltages are within acceptable limits, the CLF goes low and the device will process input drive signals. The micro-controller should monitor the CLF flag at start-up and wait for the CLF flag to go LOW before sending power pulses to the UCD7K device. 9.3.4 Driver Output The high-current output stage of the UCD7K device family is capable of supplying ±4-A peak current pulses and swings to both VDD and GND. The driver outputs follows the state of the IN pin provided that the VDD and 3V3 voltages are above their respective under-voltage lockout threshold. The drive output utilizes Texas Instruments’ TrueDrive™ architecture, which delivers rated current into the gate of a MOSFET when it is most needed during the Miller plateau region of the switching transition providing efficiency gains. TrueDrive™ consists of pullup/ pulldown circuits using bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. This hybrid output stage also allows efficient current sourcing at low supply voltages. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the external MOSFET. This means that in many cases, external-schottky-clamp diodes are not required. 9.3.5 Source/Sink Capabilities During Miller Plateau Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCD7K drivers have been optimized to provide maximum drive to a power MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate capacitance with current supplied or removed by the driver device. See Reference [1] 9.3.6 Drive Current and Power Requirements The UCD7K family of drivers can deliver high current into a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. A MOSFET is used in this discussion because it is the most common type of switching device used in high frequency power conversion equipment. UCD7100 SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021 www.ti.com 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD7100 |
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