TPS37 datasheet(9/48 Pages) TI

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7.6 Timing Requirements

At VDD(MIN) ≤ VDD ≤ VDD (MAX), CTR1/MR = CTR2/MR = CTS1 = CTS2 = open (1), output reset pull-up resistor RPU = 10 kΩ,

voltage VPU = 5.5V, and CLOAD = 10 pF. VDD and SENSE slew rate = 1V / µs. The operating free-air temperature range TA =

– 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to

either VITN or VITP).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Common timing parameters

tCTR

Reset release time delay

(CTR1/MR, CTR2/MR) (2)

VIT = 2.7 V to 36 V

CCTR1 = CCTR2 = Open

20% Overdrive from Hysteresis

100

µs

VIT = 800 mV

CCTR1 = CCTR2 = Open

20% Overdrive from Hysteresis

µs

tCTS

Sense detect time delay

(CTS1, CTS2) (3)

VIT = 2.7 V to 36 V

CCTS1 = CCTS2 = Open

20% Overdrive from VIT

µs

VIT = 800 mV

CCTS1 = CCTS2 = Open

20% Overdrive from VIT

µs

tSD

Startup Delay (4)

CCTR1/MR = CCTR2/MR = Open

(1)

CCTR1 = Reset delay channel 1, CCTR2 = Reset delay channel 2,

CCTS1 = Sense delay channel 1, CCTS2 = Sense delay channel 2

(2)

CTR Reset detect time delay:

Overvoltage active-LOW output is measure from VITP - HYS to VOH

Undervoltage active-LOW output is measure from VITN + HYS to VOH

Overvoltage active-HIGH output is measure from VITP - HYS to VOL

Undervoltage active-HIGH output is measure from VITN + HYS to VOL

(3)

CTS Sense detect time delay:

Active-low output is measure from VIT to VOL (or VPullup)

Active-high output is measured from VIT to VOH

VIT refers to either VITN or VITP

(4)

During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD before the output is in the correct state based on

VSENSE.

tSD time includes the propagation delay (CCTR1 = CCTR2 = Open). Capaicitor in CCTR1 or CCTR2 will add time to tSD.

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TPS37

SNVSBJ1D – OCTOBER 2020 – REVISED DECEMBER 2021

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