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SOLOMON
SSD1820A/21
29
REV 1.4
01/03
TABLE 4a. Parallel Timing Characteristics (TA=-40 to 85°C, VDD=2.7V, VSS=0V)
Symbol
Parameter
Min
Typ
Max
Unit
tcycle
Clock Cycle Time (write cycle)
66
-
-
ns
tAS
Address Setup Time
0
-
-
ns
tAH
Address Hold Time
0
-
-
ns
tDSW
Write Data Setup Time
10
-
-
ns
tDHW
Write Data Hold Time
2
-
-
ns
tDHR
Read Data Hold Time
10
-
-
ns
tOH
Output Disable Time
-
-
30
ns
tACC
Access Time (RAM)
Access Time (Command)
-
-
-
-
80
25
ns
ns
PWCSL
Chip Select Low Pulse Width (read RAM)
Chip Select Low Pulse Width (read Command)
Chip Select Low Pulse Width (write)
95
40
15
-
-
-
-
ns
ns
PWCSH
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
30
30
-
-
-
-
ns
ns
tR
Rise Time
-
-
10
ns
tF
Fall Time
-
-
10
ns
Figure 2a. Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L)
Valid Data
tcycle
tDSW
tAS
tAH
tDHR
tACC
CS
D/ C
D0-D7
RD (E)
Valid Data
D0-D7
(Write data to driver)
(Read data from driver)
tDHW
PWCSL
PWCSH
tF
tR
tOH
WR (R/W)
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