28 / 43 page
SSD1820A/21
28
REV 1.4
01/03
SOLOMON
TABLE 3b. Parallel Timing Characteristics (TA=-40 to 85°C, VDD=1.8V, VSS=0V)
Symbol
Parameter
Min
Typ
Max
Unit
tcycle
Clock Cycle Time (write cycle)
80
-
-
ns
tAS
Address Setup Time
0
-
-
ns
tAH
Address Hold Time
0
-
-
ns
tDSW
Write Data Setup Time
15
-
-
ns
tDHW
Write Data Hold Time
5
-
-
ns
tDHR
Read Data Hold Time
15
-
-
ns
tOH
Output Disable Time
-
-
40
ns
tACC
Access Time (RAM)
Access Time (command)
-
-
-
-
100
35
ns
ns
PWCSL
Chip Select Low Pulse Width (read RAM)
Chip Select Low Pulse Width (read Command)
Chip Select Low Pulse Width (write)
120
55
20
-
-
-
-
-
-
ns
ns
ns
PWCSH
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
40
40
-
-
-
-
ns
ns
tR
Rise Time
-
-
10
ns
tF
Fall Time
-
-
10
ns
Valid Data
tcycle
tDSW
tAS
tAH
tDHR
tACC
CS
D/C
D0-D7
E
Valid Data
D0-D7
(Write data to driver)
(Read data from driver)
tDHW
PWCSL
PWCSH
tF
tR
R/W
tOH
Figure 1b. Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H)
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
