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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADIN1300BCPZ-R7 датащи(PDF) 33 Page - Analog Devices |
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ADIN1300BCPZ-R7 датащи(HTML) 33 Page - Analog Devices |
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33 / 79 page  Data Sheet ADIN1300 Rev. 0 | Page 33 of 79 N by 8 minus 1 cycles register (SOP_N_8_CYC_M_1_D_EN register, Address 0x9428, Bits[6:4]). The ADIN1300 start of packet detection and indication circuit includes the ability to delay each of the SOP transmit and receive indications by a programmable number of clock cycles. The purpose of this on the receive side is to support MAC interfaces with long latency so that the received frame SOP indication is not asserted before the MAC receives the frame. The purpose of this on the transmit side is to align the transmit SOP indication assertion close to the reference point set on the MDI pins (so that the time stamping point does not have to be adjusted at the MAC/switch side). There are programmable registers for the delays for 1000BASE-T mode, 100BASE-TX mode, and 10BASE-T mode for transmit and receive. These are programmed via the SOP_RX_DEL register and SOP_TX_DEL register, Address 0x9429 and Address 0x942A, respectively. |
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