ADIN1300BCPZ-R7 datasheet(24/79 Pages) AD

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ADIN1300

Data Sheet

Rev. 0 | Page 24 of 79

PHY OUTPUT CLOCKS

The following internal PHY clock signals can be made available

at the GP_CLK pin:

•

125 MHz free running clock

•

125 MHz recovered clock

•

25 MHz clock

•

25 MHz or 125 MHz free running clock

•

25 MHz or 125 MHz recovered clock

This is configured in through register writes via the

GE_CLK_CFG register, Address 0xFF1F. By default, the PHY

clock is off. Note that selecting the 125 MHz free running clock

has an impact on power consumption, as the CMU is always

powered up except during reset and power up.

POWER SUPPLY DOMAINS

The ADIN1300 has the following three power supply domains

and requires a minimum of two supply sources, 0.9 V and 3.3 V:

•

DVDD_0P9 is the 0.9 V digital core power supply input.

•

AVDD_3P3 is the 3.3 V analog power supply input for the

PHY MDI interface, analog circuitry, XTAL oscillator,

DLL, RESET_N, CLK25_REF generation, and LED circuitry.

•

VDDIO enables the MDIO and MAC interface voltage

supply to be configured independently of the other circuitry

on the ADIN1300. In most cases, RMII/MII is operated at

3.3 V and RGMII is operated at 2.5 V, but the MAC interface

can operate at 3.3 V, 2.5 V, or 1.8 V to allow the MAC

interface to run at a lower voltage and power if the MAC

supports this.

There are no power supply sequencing requirements around the

order of power being applied to the device. See the Power-Up

Timing section for more details.

PHY CORE

RMII REF_CLK

GP_CLK

CLK25_REF

ADIN1300

XTAL_I/CLK_IN/REF_CLK

125MHz FREE RUNNING CLOCK

125MHz RECOVERED CLOCK

25MHz CLOCK

25MHz/125MHz FREE RUNNING CLOCK

25MHz/125MHz RECOVERED CLOCK

XTAL_O

XTAL

OSCILLATOR

Figure 26. PHY Output Clocks Simplified Diagram

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