Page 16

ams Datasheet

Document Feedback

[v2-00] 2021-Apr-19

AS5013 − Detailed Description

Note(s):

1. For bus line loads CB between 100pF and 400 pF the timing parameters must be linearly interpolated.

2. After this time the first clock is generated.

3. A device must internally provide a minimum hold time (300n for Fast-mode, 80ns / max 150ns for High-speed mode) for the SDA

signal (referred to the VIHmin of the SCL) to bridge the undefined region of the falling edge of SCL.

4. A fast-mode device can be used in standard-mode system, but the requirement tSU;DAT = 250ns must then be met. This is

automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period

of the SCL signal, it must output the next data bit to the SDA line tRmax + tSU;DAT = 1000 + 250 = 1250ns before the SCL line is released.

I²C Modes

The AS5013 supports the I²C bus protocol. A device that sends

data onto the bus is defined as a transmitter and a device

receiving data as a receiver. The device that controls the

message is called a master. The devices that are controlled by

the master are referred to as slaves. A master device that

generates the serial clock (SCL), controls the bus access, and

generates the START and STOP conditions must control the bus.

Rise time of

SCLH signal

External

pull-up

source of

3mA

-

-

10

40

20

80

ns

Rise time of

SCLH signal

after

repeated

START

condition

and after an

acknowledg

e bit

External

pull-up

source of

3mA

-

-

10

80

20

160

ns

Rise Time of

SDA and SCL

Signals

120

-

-

-

-

ns

Fall time of

SDA and SCL

signals

120

-

-

-

-

ns

Setup Time

for STOP

Condition

600

-

160

-

160

-

ns

Noise

margin at

LOW level

For each

connected

device

(including

hysteresis)

0.1VDDp

-

0.1

VDDp

-

0.1

VDDp

-V

Noise

margin at

HIGH level

0.2VDDp

-

0.2

VDDp

-

0.2

VDDp

-V

Symbol

Parameter

Condition

Fast-Mode

HS-Mode

HS-Mode

Unit

Min

Max

Min

Max

Min

Max