AS3955 datasheet(73/102 Pages) AMSCO

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ams Datasheet

Page 73

[v1-04] 2016-Feb-03

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AS3955 − Detailed Description

Interrupt Interface Description

There are two interrupt registers implemented in AS3955

(Interrupt Register 0 and Interrupt Register 1).

When an interrupt condition is met, the source of interrupt bit

is set in the interrupt register and the IRQ pin goes to high.

The microcontroller shall read the interrupt registers to

distinguish between different interrupt sources. After an

interrupt register is read, its content is reset to 0. IRQ pin goes

to low after the interrupt bit(s), which caused its transition to

high, has been read. Please note that there may be multiple

interrupt register bits set in case the controller does not

immediately read the Interrupt Registers after the IRQ signal

was set and another event causing interrupt occurred.

The process of reading interrupt registers is composed of two

phases. In the first phase, interrupts are pushed into internal

buffer just before reading the first bit of the register. In the

second phase the bits stored in the buffer are read out. The

interrupts stored in each internal register are cleared and

considered being read out at the rising edge of SCLK of the first

interrupt bit for each interrupt register.

Buffer Interrupts and Buffer Status Register

The AS3955 contains a 32 byte buffer. In case of transmission

the Control logic shifts data which was previously loaded by the

external controller to the Framing Block and further to the

Transmitter. During reception, the demodulated data is stored

in the buffer and the external controller can download received

data.

Transmit and receive capability of the AS3955 is limited by the

buffer size. The maximum message size that can be received or

transmitted is 32 bytes. The mutual access to the buffer from

NFC block and SPI / I²C block is not allowed. At the beginning

of each reception the buffer is cleared automatically. Before the

data is loaded into the buffer via SPI / I²C for transmission the

MCU must take care of clearing the buffer.

Five interrupts that can be triggered during read or write of the

buffer:

• When buffer overflow or underflow is detected an I_bf_

err is triggered. The reason for the interrupt can be

distinguished by reading the Buffer Status Register 1.

• Buffer overflow IRQ is not blocked, in case if more than 32

bytes are received from reader or written via SPI / I²C into

buffer the buffer underflow IRQ is produced.

• When data is loaded via data RF an I_rxs and I_rxe are

triggered

• When all data is transmitted an I_txe is triggered

• When buffer is already busy due to another operation in

progress and MCU tries to access the internal buffer an

interrupt I_acc_err shall be triggered.

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