AS3911 datasheet(53/159 Pages) AMSCO

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ams Datasheet

Page 53

[v2-11] 2016-Jun-13

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AS3911 − Application Information

Direct command chaining is not allowed since this command

clears all registers.

IRQ due to termination of direct command is not produced.

Clear

This direct command stops all current activities (transmission

or reception), clears FIFO, clears FIFO Status Registers and stops

all timers except Wake-up timer (in case bit nrt_emv in the

General Purpose and No-Response Timer Control Register is set

to one, the No-response timer is not stopped). It also clears

collision and interrupt registers. This command has to be sent

first in a sequence preparing a transmission before writing data

to be transmitted in FIFO (except in case of direct commands

Transmit REQA and Transmit WUPA).

This command is accepted in case en (bit 7 of the Operation

Control Register) is set and Xtal oscillator frequency is stable.

Direct command chaining is possible.

IRQ due to termination of direct command is not produced.

Transmit Commands

All Transmit commands (Transmit With CRC, Transmit Without

CRC, Transmit REQA and Transmit WUPA) are only accepted in

case the Transmitter is enabled (bit tx_en is set).

Before sending commands Transmit With CRC and Transmit

Without CRC direct command Clear has to be sent, followed by

definition of number of transmitted bytes and writing data to

be transmitted in FIFO.

Direct commands Transmit REQA and Transmit WUPA are used

to transmit ISO14443A commands REQA and WUPA

respectively. Sending command Clear before these two

commands is not necessary.

The number of valid bits in the last byte must be set to zero

(nbtx<2:0> in the Number of Transmitted Bytes Register 2) prior

to executing Transmit REQA or Transmit WUPA.

Direct command chaining is possible.

IRQ due to termination of direct command is not produced.

AS3911 датащи(PDF) 53 Page - ams AG