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AS3911 датащи(PDF) 84 Page - ams AG |
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AS3911 датащи(HTML) 84 Page - ams AG |
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84 / 159 page ![]() Page 84 ams Datasheet Document Feedback [v2-11] 2016-Jun-13 AS3911 − Application Information Mask Receive Timer Register Figure 64: Mask Receive Timer Register Note(s): 1. Default setting is set at power-up and after Set Default command. 2. In NFCIP-1 bit rate detection mode, the clock of the Mask Receive timer is additionally divided by eight (one count is 512/fc) to cover range up to ~9.6 ms. Address 0Eh: Mask Receive Timer Register Type: RW Bit Name Default Function Comments 7mrt7 0 Defined in steps of 64/fc (4.72 μs). Range from 256/fc (~18.88 μs) to 16320/fc (~1.2 ms) Timeout = mrt<7:0> * 64/fc Timeout (0 ≤ mrt<7:0> ≤ 4) = 4 * 64/fc (18.88 μs) In NFCIP-1 bit rate detection mode one step is 512/fc (37.78 μs) Defines time after end of Tx during which receiver output is masked (ignored). For the case of ISO14443A 106 kbit/s the Mask Receive Timer is defined according to PCD to PICC frame delay time definition, where mrt<7:0> define number of n/2 steps. Minimum mask receive time of 18.88 μs covers the transients in receiver after end of transmission. 6mrt6 0 5mrt5 0 4mrt4 0 3mrt3 1 2mrt2 0 1mrt1 0 0mrt0 0 |
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