AS5132 datasheet(21/40 Pages) AMSCO

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[v2-06] 2016-Jan-26

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AS5132 − Detailed Description

Pulse Width Modulation (PWM) Output

The AS5132 provides a pulse width modulated output (PWM),

whose duty cycle is proportional to the absolute angle position.

Figure 29 shows the output format. In case of an internal error

the high pulse contains 12 steps. An error can be easily

identified by the external microcontroller. The zero degree

angle position is build with 16 steps (12 + 4) high and 359 steps

low followed by 8 exit steps.

Figure 27:

PWM Output

PWM External Clock

The PWM period depends on the setting of the OTP bit Ext. CLK

EN. By default the internal clock source is used as a reference.

An external clock can be connected to the pin COM/INC.

In case Ext. CLK EN is set, the output-mode which is

determined by the states of {COM/INC, Test3, Test2, Test1, Test0}

Figure 31 on page 23 during start-up is overwritten and U,V,W

commutation mode signals are activated.

After internal power on reset (POR_en), the OTP is read out.

When the Ext. CLK EN is programmed successfully, the COM/INC

pin is used as external clock for the PWM block. After 4 clock

cycles of Ext. CLK EN, the reset of TADC (TADC_rst) and the PWM

block is released.

*PWM output pin is connected internally to the VDDP voltage domain. VDD and VDDP can be separately

connected

** Recommended pull-up (typ. 10kOhm). Floating state of a digital input in an application is not allowed

***Depending on the use case:

- Application use case (connection to VDD or leave unconnected. Capacitive load during operation and

startup not allowed)

- Programming use case (see Figure 24)

VDD

Micro-

Controller

VSS

AS5132

Typ. 10kOhm**

CSN

VDDP* VDD

CLK

VSS

+5V

VDD

100nF

Input

PWM

PROG***

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