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AS5132 датащи(PDF) 9 Page - ams AG |
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AS5132 датащи(HTML) 9 Page - ams AG |
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9 / 40 page ![]() ams Datasheet Page 9 [v2-06] 2016-Jan-26 Document Feedback AS5132 − Electrical Characteristics DC Characteristics of Digital Outputs Figure 11: CMOS Outputs S, U_A, V_B, W_I, PWM, DIO Timing Characteristics Figure 12: Timing Characteristics Symbol Parameter Min Max Units Note VOH High level output voltage VDDP-0.5 VDDP V PWM and S have 8mA output load, DIO has 4mA output load. VDD-0.5 VDD U_A, V_B, W_I have 4mA output load. VOL Low level output voltage 0 VSS+0.4 V PWM and S have 8mA output load, DIO, U_A, V_ B, W_I has 4mA output load. CL Capacitive load 35 pF Symbol Parameter Min Typ Max Units fCLK Clock frequency normal operation 5 6 MHz fCLKP Clock frequency during OTP programming 200 650 kHz t1 CSn to positive edge of CLK 150 ns t2 CSn to drive bus externally 0 ns t3 Setup time command bit (data valid to positive edge of CLK) 50 ns t4 Hold time command bit (data valid after positive edge of CLK) 15 ns t5 Float time (positive edge of CLK for last command bit to bus float) 0.5 *1/fCLK ns t6 Bus driving time (positive edge of CLK for last command bit to bus drive) 0.5 *1/fCLK ns t7 Data valid time (positive edge of CLK to bus valid) 0.5 *1/fCLK 0.5 *1/fCLK + 50 ns t8 Hold time data bit (data valid after positive edge of CLK) 0.5 *1/fCLK ns |
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