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SH7041A датащи(PDF) 190 Page - Renesas Technology Corp

номер детали SH7041A
подробное описание детали  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A датащи(HTML) 190 Page - Renesas Technology Corp

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Table 8.6
Execution State of DTC
Mode
Vector Read I
Register
Information
Read/Write J
Data Read K
Data Write L
Internal
Operation M
Normal
1
7
1
1
1
Repeat
1
7
1
1
1
Block transfer
1
7
N
N
1
Note:
N: block size (default set values of DTCRB)
Table 8.7
State Counts Needed for Execution State
Access Objective
On-
chip
RAM
On-
chip
ROM
Internal I/O
Register
External Device
Bus width
32
32
32
8
16
32
Access
state
11
2*
1
3*
2
22
2
Execution
Vector read
S
I
—1
—
4
2
2
state
Register information
read/write
S
J
11
—
8
4
2
Byte data read
S
K
11
23
22
2
Word data read
S
K
11
23
42
2
Long word data read
S
K
11
46
84
2
Byte data write
S
L
11
23
22
2
Word data write
S
L
11
23
42
2
Long word write
S
L
11
46
84
2
Internal operation
S
M
1
Notes: *1 Two state access module : port, INT, CMT, SCI, etc.
*2 Three state access module : WDT, CACHE, UBC, etc.
The execution state count is calculated using the following formula.
∑ indicates the number of
transfers by one activating source (count + 1 when CHNE bit is 1).
Execution state count = I · S
I + ∑ (J · SJ + K · SK + L · SL) + M · SM



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