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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SH7041A датащи(PDF) 189 Page - Renesas Technology Corp |
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SH7041A датащи(HTML) 189 Page - Renesas Technology Corp |
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189 / 923 page  151 Table 8.5 Block Transfer Mode Register Functions Register Function Values Written Back upon a Transfer Information Write DTMR Operation mode control DTMR DTCRA Transfer count DTCRA – 1 DTCRB Block length (Not written back) DTSAR Transfer source address (DTS = 0) Increment/ decrement/ fixed (DTS = 1) DTSAR initial value DTDAR Transfer destination address (DTS = 0) DTDAR initial value (DTS = 1) Increment/ decrement/ fixed 8.3.8 Operation Timing Figure 8.6 shows a DTC operation timing example. Activating source DTC request Address Vector read Data transfer Transfer information read Transfer information write R W φ Figure 8.6 DTC Operation Timing Example (Normal Mode) When register information is located in on-chip RAM, each mode requires 4 cycles for transfer information reads, and 3 cycles for writes. 8.3.9 DTC Execution State Counts Table 8.6 shows the execution state for one DTC data transfer. Furthermore, table 8.7 shows the state counts needed for execution state. |
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