SH7041A datasheet(169/923 Pages) RENESAS

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Instruction execution: TRAPA instruction execution

→ Branch destination instruction

execution

3. Conditional delay branch instruction, branch taken: BT/S, BF/S

Instruction fetch cycles: Conditional delay branch instruction fetch

→ Next-instruction

fetch (delay slot)

→ Next-instruction overrun fetch → Branch destination instruction

fetch

Instruction execution: Conditional delay branch instruction execution

→ Delay slot

instruction execution

→ Branch destination instruction execution

When a conditional branch instruction or TRAPA instruction causes a branch, the branch

destination will be fetched after the next instruction or the one after that does an overrun fetch.

However, because the instruction that is the object of the break first breaks after a definite

instruction fetch and execution, the kind of overrun fetch instructions noted above do not

become objects of a break. If data access breaks are also included with instruction fetch breaks

as break conditions, a break occurs because the instruction overrun fetch is also regarded as

becoming a data break.

7.5.3

Contention between User Break and Exception Handling

If a user break is set for the fetch of a particular instruction, and exception handling with higher

priority than a user break is in contention and is accepted in the decode stage for that instruction

(or the next instruction), user break exception handling may not be performed after completion of

the higher-priority exception handling routine (on return by RTE).

Thus, if a user break condition has been set for the fetch of the branch destination instruction

following a branch (BRA, BRAF, BT, BF, BT/S, BF/S, BSR, BSRF, JMP, JSR, RTS, RTE,

exception handling), and exception handling for this branch destination instruction with a higher

priority than a user break interrupt is accepted, user break exception handling will not be

performed after completion of that exception handling routine.

Therefore, a user break condition must not be set for the fetch of the branch destination instruction

following a branch.

7.5.4

Break at Non-Delay Branch Instruction Jump Destination

When a branch instruction with no delay slot (including exception handling) jumps to the jump

destination instruction on execution of the branch, a user break will not be generated even if a user

break condition has been set for the first jump destination instruction fetch.

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