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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SH7041A датащи(PDF) 168 Page - Renesas Technology Corp |
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SH7041A датащи(HTML) 168 Page - Renesas Technology Corp |
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168 / 923 page  130 7.4.3 Break on DMA/DTC Cycle 1. Register settings: UBARH = H'0076 UBARL = H'BCDC UBBR = H'00A7 Conditions set: Address: H'0076BCDC Bus cycle: DMA/DTC, data access, read, longword A user break interrupt occurs when longword data is read from address H'0076BCDC. 2. Register settings: UBARH = H'0023 UBARL = H'45C8 UBBR = H'0094 Conditions set: Address: H'002345C8 Bus cycle: DMA/DTC, instruction fetch, read (operand size not included in conditions) A user break interrupt does not occur because no instruction fetch is performed in the DMA/DTC cycle. 7.5 Cautions on Use 7.5.1 On-Chip Memory Instruction Fetch Two instructions are simultaneously fetched from on-chip memory. If a break condition is set on the second of these two instructions but the contents of the UBC break condition registers are changed so as to alter the break condition immediately after the first of the two instructions is fetched, a user break interrupt will still occur when the second instruction is fetched. 7.5.2 Instruction Fetch at Branches When a conditional branch instruction or TRAPA instruction causes a branch, instructions are fetched and executed as follows: 1. Conditional branch instruction, branch taken: BT, BF Instruction fetch cycles: Conditional branch instruction fetch → Next-instruction overrun fetch → Next-instruction overrun fetch → Branch destination instruction fetch Instruction execution: Conditional branch instruction execution → Branch destination instruction execution 2. TRAPA instruction, branch taken: TRAPA Instruction fetch cycles: TRAPA instruction fetch → Next-instruction overrun fetch → Next-instruction overrun fetch → Branch destination instruction fetch |
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