LTC4261 datasheet(13/74 Pages) AD

13 / 74 page

LTC4283

Rev. B

For more information www.analog.com

PIN FUNCTIONS

ADIN1 – ADIN4 (Pins 7 – 10): ADC Inputs. A single-ended

voltage between 0V and 2.048V applied to each ADIN

is measured by the on-chip ADC. Two differential volt-

ages ADIN2 – ADIN1 and ADIN4 – ADIN3, if enabled, are

also measured by the ADC with a full scale of 32.768mV.

Connect to VEE if unused.

ADIO1 – ADIO4 (Pins 20 – 23): General Purpose Inputs/

Outputs and ADC Inputs. Configurable to logic inputs and

general purpose outputs (open-drain). See Table 13 for

details. The single-ended voltages at ADIOs are measured

by the ADC with a full scale of 2.048V. The differential volt-

ages ADIO2 – ADIO1 and ADIO4 – ADIO3, if enabled, are

also measured by the ADC with a full scale of 32.768mV.

Connect to VEE if unused.

ADR0, ADR1 (Pin 33, Pin 34): Serial Bus Address Inputs.

Connecting to VEE, OPEN or INTVCC configures one of nine

possible addresses, with one dedicated to the single-wire

broadcast mode. Do not bias with an external supply. See

Table 1 in Applications Information for address decoding.

ALERT# (Pin 29): Fault Alert Output. Open-drain logic

output that pulls to VEE when a fault occurs to alert the

host controller. A fault alert is enabled by the FAULT_

ALERT and ADC_ALERT registers. See Tables 15 and 16

in Applications Information for details. Connect to VEE if

unused.

DRAIN (Pin 15): Drain Sense Input. Connect an external

100k resistor between this pin and the drain terminal of

the N-channel MOSFET. A DRAIN voltage below 2.048V is

one of the conditions to assert power good outputs. When

DRAIN voltage is above a voltage configurable between

72mV and 203mV, the FET Bad fault timer is started and

the TMR output current is enabled when not in current

limit. DRAIN is internally clamped to a minimum of 3.2V.

DRNS (Pin 16): Attenuated Drain Sense Input. Connect to

the tap of an external resistive divider between the drain

terminal of the N-channel MOSFET and VEE to monitor

the drain voltage. DRNS coupled with RTNS monitors the

output voltage for the load, which controls dV/dt inrush

current and current limit foldback. DRNS operates from

0 to 2.8V. Connect to VEE if unused.

EN# (Pin 1): Device Enable Input. Pull low to enable the

GATE output to turn-on after a startup debounce delay.

When pulled high, GATE is turned off. A high-to-low tran-

sition clears faults. Transitions are recorded. Requires

external pull-up. Debouncing with an external capacitor

is recommended when used to monitor board present.

Connect to VEE if unused.

Exposed Pad (Pin 39): Exposed Pad may be left open or

connected to device ground (VEE).

GATE (Pin 14): N-Channel MOSFET Gate Drive Output.

GATE is pulled high by internal current sources (>80μA)

when VIN and INTVCC cross the UVLO thresholds, UV and

OV conditions are satisfied, no other faults are present

and the debounce delay expires. The GATE voltage higher

than VIN – 1.8V satisfies one of the conditions to assert

power good outputs. Upon a low impedance output short,

a 2.3A fast pull-down current is immediately activated.

INTVCC (Pin 36): 5V Internal Supply Output. The output of

the internal linear regulator sources up to 30mA with an

UVLO threshold of 4V. The supply powers the data con-

verters, logic control circuitry, I2C interface and EEPROM.

Bypass with 1μF capacitor to VEE. INTVCC is not current

limited. When driving INTVCC with an external supply, VIN

and VZ must be left open or connected to INTVCC.

OV (Pin 4): Overvoltage Detection Input. Connect to an

external resistive divider from VEE. When OV is above its

threshold of 1.406V, the GATE output pulls low to turn

off the MOSFET and an overvoltage fault is recorded. The

overvoltage fault does not affect the status of the power

good outputs. Connect to VEE if unused.

PGIO1, PGIO2 (Pin 24, Pin 25): General Purpose

Inputs/Outputs. Configurable to sequenced, inverted

and non-inverted power good outputs, general purpose

logic inputs and open-drain outputs. See Table 12 in

Application Information for details. If the PGIO2_ACLB

bit in CONTROL_1 register 0x0A is set, PGIO2 is config-

ured as inverted current limit engagement indicator after

startup. Connect to VEE if unused.

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