LTC4261 datasheet(39/74 Pages) AD

39 / 74 page

LTC4283

Rev. B

For more information www.analog.com

APPLICATIONS INFORMATION

Three resistors of 2.25mΩ each would give the correct

sense resistance. The closest next-larger available sense

resistor value is 3mΩ:

RS=

3mΩ

=1mΩ

Adjust the sense voltage to 20mV to restore the current by

setting the ILIM bits in CONFIG_1 register 0X0D to 0101b:

ILIM =

VILIM

20mV

1mΩ

= 20A

Recompute the sense power:

PS =20mV • 20A = 400mW

The power dissipation of each resistor package is now

400mW/3 = 133mW, still an acceptable value for 1206

resistors. Sense voltage may need to be readjusted to

account for current sensing inaccuracies such as contact

and copper trace resistances, as explained in Example 1,

Step 1.

Step 2. Select resistive dividers for DRNS (drain sense),

RTNS (RTN sense) and VOUTTH (output low reference).

See Example 1, Step 2 for detailed design considerations.

First compute the divider ratio r for RTNS and DRNS:

VS(MAX)

1.8V

52.8V

1.8V

= 29.3

Standard values of 280kΩ and 10kΩ give a divider ratio of

29. The ADC measurement full-scale for input (at RTNS)

and MOSFET drain (at DRNS) voltages is

VFS(MEAS) = r • 2.048V = 29 • 2.048V = 59.4V

which gives a LSB size of 14.5mV in 12-bit mode.

With VLOAD = 29 • 1.8V = 52.2V corresponding to

RTNS – DRNS = 1.8V, the current limit starts to fold back

when VLOAD drops below 26.1V in overload conditions.

There is no foldback at normal input between −43.2V

and −52.8V, allowing the MOSFETs to pass the full load

current.

If 40V is chosen as the output voltage threshold to reset

power good signals, with a divider ratio of 29 on DRNS

and RTNS, the VOUTTH threshold is 40V/29 = 1.379V. This

voltage can be obtained with a resistive divider between

INTVCC (5V) and VEE. The divider ratio is 5V/1.379V =

3.63. A divider of 26.7k and 10.2k as shown Figure 13

gives a close enough ratio of 3.62.

Step 3. Design the TMR behavior. See Example 1, Step 3

for general design considerations. Since there is no con-

cern about a large input step after startup, a very short

timer delay is needed for MOSFET turn-off upon a fault

such as output short-circuit. Therefore, the TMR function

is essentially a filtered circuit breaker and a single timer

capacitor on TMR works just fine for this purpose.

It has been found that 20μs of circuit breaker filtering is

sufficient to reject noise encountered in most systems.

The TMR pull-up current is 202μA at maximum overload,

with a voltage threshold of 2.048V. Compute the timer

capacitance, Ct, for 20μs filter delay:

Ct=

ITMR(UP),MAX • tFILTER

VTMR(TH)

202µA • 20µs

2.048V

=2nF

Select the closest next-larger available capacitance:

Ct = 2.2nF. With single capacitor on TMR, the THERM_

TMR bit in CONTROL_1 register 0x0A must be cleared to

enable the internal 2μA pull down current. Additionally, the

FB_DIS bit in CONTROL_1 register 0x0A should be cleared

to keep foldback enabled after startup to protect MOSFET

from damage upon a low impedance short-circuit.

Step 4. Design the startup current and FET bad timer.

Since in Step 3 the TMR function is designed as a short

circuit-breaker delay, it is desired to use the dV/dt startup

mode so that a small trickle current charges the load

capacitance without triggering current limit. (see dis-

cussions in Example 1, Step 5). The design procedure

involves selecting a RAMP capacitor to set the dV/dt rate

for desired charging current, selecting a proper startup

current limit and checking the temperature rise of the

MOSFET under a resistive short condition.

Choice of the charging current is a trade-off between

maximum charging time and peak temperature of the

MOSFET. As discussed in Example 1, Step 5, the charging

current should be set to a low level that is just necessary

to achieve the required charging time. Suppose an upper

limit of 300ms charging time is desired for a 1000μF load

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