LTC4261 datasheet(42/74 Pages) AD

42 / 74 page

LTC4283

Rev. B

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APPLICATIONS INFORMATION

to the I2C master, this allows the master to issue a com-

mand that power cycles the entire board, including itself.

Once set, the RBT_EN bit remains 1 after reboot is com-

pleted. Clear it before issuing the next reboot command.

Data Converters

The LTC4283 incorporates a pair of Sigma-Delta A/D

converters (ADCs) that are configurable from 8-bit at

1kHz conversion rate to 16-bit at 1Hz conversion rate

in five settings using the ADC bits in PGIO_CONFIG_2

mode, the first ADC (ADC1) continuously monitors the

input current through a sense resistor between SENSE+

and SENSE−. The second ADC (ADC2) is synchronized to

ADC1 and monitors VPWR for power multiplication plus

one of the 14 auxiliary inputs. VPWR is selectable between

the attenuated input voltage at RTNS and the attenuated

MOSFET drain voltage at DRNS using the VPWR_SELECT

bit in CONFIG_3 register 0x0F. The auxiliary inputs include

10 single-ended signals and 4 differential signals and

are selectable using ADC_SELECT registers 0x13-0x14

(see Table 14). If multiple auxiliary inputs are selected,

ADC2 will rotate between them in the continuous mode

as illustrated in Figure 15. The AUX_ADC_CH bits in ADC_

STATUS register 0x01 are refreshed at the end of each

conversion to indicate the auxiliary input that completed

the latest measurement (see Table 5). If all bits in ADC_

SELECT registers 0x13–0x14 are cleared while the ADCs

are running in continuous mode, ADC1 and ADC2 con-

tinue to measure SENSE+ − SENSE− and VPWR (RTNS or

DRNS), respectively. The auxiliary measurements of ADC2

are disabled and the data in 0x41–0x79 from the previous

measurement are preserved except 0x4A (ADIN1), which

is overwritten by a small number.

The full-scale voltage of any single-ended input is 2.048V.

For each differential input, one terminal must be at the

same potential of VEE. Normally the negative terminal is at

VEE and the full-scale is 32.768mV. If the positive terminal

is at VEE, the full scale becomes 33.301mV. When using

ADIN1–ADIN4 and ADIO1–ADIO4 as differential inputs,

ADIN1, ADIN3, ADIO1 and ADIO3 must be the negative

terminals, and ADIN2, ADIN4, ADIO2, ADIO4 must be

positive terminals, respectively. Note that for each reso-

lution setting, the resolution of differential auxiliary inputs

of ADC2 is one bit less than that of the SENSE+ − SENSE−

input of ADC1 or the single-ended inputs.

After each conversion of the two synchronized ADCs, the

measured current sense voltage (SENSE+ − SENSE−) is

multiplied by the measured VPWR (RTNS or DRNS) volt-

age to calculate input power or MOSFET power, configu-

rable using the VPWR_SELECT bit in CONFIG_3 register

0x0F. All measured results and calculated power are stored

to corresponding data registers (see Table 3). They are

also compared to the minimum and maximum values that

are stored in the minimum and maximum data registers. If

the measurement is a new minimum or maximum value,

then the corresponding minimum or maximum data reg-

isters are updated. Note that all ADC data registers from

0x41 to 0x79 have a length of two bytes or 16 bits, and

the data for all resolutions are left justified.

The ADC measurements are compared to the 8-bit mini-

mum and maximum alarm thresholds that are config-

ured using registers 0x1B through 0x40 and will set the

ROTATION SEQUENCE OF AUXILIARY INPUTS SELECTED BY ADC_SELECT REGISTERS 0x13-0x14

TIME

ADIN1-4

ADIO1-4

DRNS

DRAIN

RESERVED

ADIN2 – ADIN1

ADIN4 – ADIN3

ADIO2 – ADIO1

ADIO4 – ADIO3

• • •

ADC1

• • •

ADC1

• • •

SENSE+ – SENSE−

• • •

ADC2

• • •

ADC2

• • •

AUX1

VPWR

AUX2

VPWR

AUXN

VPWR

AUX1

VPWR

Figure 15. LTC4283 ADC Measurement Pattern in Continuous Mode

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