IMX7ULPIECB2 datasheet(13/112 Pages) NXP

13 / 112 page

Table 1. i.MX 7ULP modules list (continued)

Block Name

Block Mnemonic

Subsystem

Power

Domain

Brief description

LCD Interface

Controller

LCDIF

Multimedia

The LCDIF is a general purpose display

controller used to drive a wide range of

display devices varying in size and

capabilities. The LCDIF is used as a

bridge between the DSI controller and

the NIC0 crossbar.

Low-Leakage Wake-

Up Unit

LLWU

System Control

DGO

The Low-Leakage Wake-Up Unit

(LLWU) module allows user to select up

to 32 external pin sources and up to 8

internal modules as a wakeup source

from low leakage power modes.

Low Power Inter-

Integrated Circuit

LPI2C0-7

Connectivity and

Communications

AD, RT

The Low Power Inter-Integrated Circuit

(LPI2C) module implements an efficient

interface to an I2C bus as a master. The

LPI2C can continue operating while the

processor is in stop mode provided an

appropriate peripheral clock is available.

This module is designed for low CPU

overhead with DMA offloading of FIFO

in the real-time domain. LPI2C4 -

LPI2C7 are in the application domain.

Low Power Periodic

Interrupt Timer

LPIT0-1

Timers

AD, RT

Low Power Periodic Interrupt Timer

(LPIT) is a multichannel timer module

that can generate independent pre-

trigger and trigger outputs. These timer

channels can operate individually or can

be chained together. The pre-trigger

and trigger outputs can be used to

trigger other modules on the device.

The LPIT can also operate in low power

modes. LPIT0 is in the real-time

domain. LPIT1 is in the application

domain.

Low Power Serial

Peripheral Interface

LPSPI0-3

Connectivity and

Communications

AD, RT

The Low Power Serial Peripheral

Interface (LPSPI) module implements

an efficient interface to an SPI bus as a

master and/or a slave. The LPSPI can

continue operating while the processor

is in stop mode if an appropriate

peripheral clock is available. This

module is designed for low CPU

overhead with DMA offloading of FIFO

are in the real-time domain. LPSPI2 and

LPSPI3 are in the application domain.

Low-power Trusted

Cryptography

LTC

Security

Low-power Trusted Cryptography is an

architecture that allows multiple

cryptographic hardware accelerator

engines to be instantiated and share

Table continues on the next page...

i.MX 7ULP modules list

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

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