IMX7ULPIECB2 datasheet(39/112 Pages) NXP

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USBPHY_USB1_VBUS_DETECTn[VBUSVALID_SEL] selects which option is used. If the VBUS_VALID comparator is

used, USBPHY_USB1_VBUS_DETECTn[VBUSVALID_THRESH] determines the threshold voltage for a valid VBUS.

The programmable range is 4.0V to 4.4V (default).

21. The 7ULP USB PHY provides two options for reporting VBUS valid back to the USB controller:

• A programmable internal VBUS_VALID comparator (the default option), or

• An alternate VBUS_VALID_3V detector that will report VBUS valid for voltages above 3 V.

USBPHY_USB1_VBUS_DETECTn[VBUSVALID_SEL] selects which option is used. If the VBUS_VALID_3V detector

is used, the detector voltage is not programmable.

7.1.6 Estimated maximum supply currents

This table represents the estimated maximum current on the power supply rails and

should be used for power supply selection. The data below is based on design

simulation as well as measured data. Note that some of the data in the table is based

on internal companion regulator limits and not actual use cases. Maximum currents

are higher by far than the average power consumption of typical use cases.

Table 6. Estimated maximum supply currents

Power rail

Conditions

Maximum currents

Unit

VDD_VBAT42

4.2 V

µA

VDD_PLL18

1.8 V

VDD18_IOREF + VDD_PMC18 +

VDD_PTB1

1.8 V

Use Maximum IO equation 2 + 10 mA

VDD18_DDR + VDD18_HSIC

1.8 V

VDD_ANA18 + VREFH_ANA18

1.8 V

µA

VDD_DSI18

1.8 V

0.6

VDD_USB18

1.8 V

High speed mode

VDD_PMC18_DIG0

1.8 V, CM4 200 MHz

VDD_PMC12_DIG1 + VDD_DIG1 +

VDD_DSI11

1.15 V

CA7 LDO Bypass Mode

CA7 500 MHz

350

1.15 V

CA7 LDO Bypass Mode

CA7 720 MHz

504

VDD_PMC12_DIG1

1.2 V

CA7 LDO Enabled Mode

CA7 500 MHz

350

1.2 V

CA7 LDO Enabled Mode

CA7 720 MHz

504

Table continues on the next page...

System specifications

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

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