IMX7ULPIECB2 datasheet(29/112 Pages) NXP

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4.2.1 Analog—real-time domain

The i.MX 7ULP Real-Time Domain implements the following analog peripherals:

• 12-bit Analog to Digital Converter

• 12-bit Digital to Analog Converter

• Comparators

See i.MX 7ULP modules list for more details.

4.2.2 Connectivity and communications—real-time domain

The i.MX 7ULP Real-Time Domain implements the following connectivity and

communications peripherals:

• Low Power Universal Asynchronous Receiver/Transmitter (LPUART)

• Low Power Inter-Integrated Circuit (LPI2C)

• Low Power Serial Peripheral Interface (LPSPI)

• Rapid General-Purpose Input and Output with 2 Ports (RGPIO2P)

• Flexible Input/Output (FlexIO)

See the i.MX 7ULP modules list for more details.

5 System control modules

5.1 JTAG—system control

Joint Test Action Group Controller (JTAGC) provides the means to test chip

functionality and connectivity while remaining transparent to system logic when not

in test mode. Testing is performed via a boundary scan technique, as defined in the

IEEE 1149.1-2001 standard.

5.2 JTAG device identification register

The device identification register (JTAG ID) allows the revision number and part

number to be read through the TAP. See the device identification register section of

the i.MX 7ULP Applications Processor Reference Manual for details. This table

shows the Part Identification Number (PIN) and the Part Revision Number (PRN) for

each i.MX 7ULP silicon revision.

System control modules

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

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