MP7651

7

Rev. 2.00

THEORY OF OPERATION

MP7651 is equipped with a serial data 3-wire standard

processor logic interface to reduce pin count, package size (28

pin), and board wire (space). This interface consists of LD which

controls the transfer of data to the selected DAC channel, SDI

(serial data/address input), CLK (shift register clock) and SDO

(serial data output). When the LD signal is high, CLK signal

loads the digital input bits (SDI) into the 16-bit shift register (8 bits

data D7 to D0, plus 4 bits address A3 to A0, and 4 bits of Chip

Select data CS0S to CS3S). If the CS0S to CS3S in the shift reg-

ister match the parallel chip-select address (CS0P to CS3P) for

the selected chip, then the LD signal going low loads the data

into the selected DAC of that chip. The LD signal going low also

disables the serial data input (SDI), output (SDO 3-stated) and

the CLK input. This design tremendously reduces digital noise,

and glitch transients into the DACs due to free running CLK and

SDI. Also, 3-stating the SDO output with LD signal would allow

read back of pre-stored digital data of the selected package us-

ing one SDO wire for all DAC ICs on the board. Note also that

referenced to GND.

D

256

AGND

(

1

)

256

()

256

()

256

255

254

+ AGND

DAC Output Voltage

)

+ AGND

+ AGND

Function

A3 A2 A1 A0

LD

CLK

RST

Shift Data In

and Out

XX

X

X

1

0

1

Repeat

Load DACs

DAC 0

0

0

0

1

DAC 1

0

0

1

0

DAC 2

0

0

1

1

DAC 3

0

1

0

0

DAC 4

0

1

0

1

DAC 5

0

1

1

0

DAC 6

0

1

1

1

DAC 7

1

0

0

0

1

1

1

1

1

1

1

X

X

X

Table 1. Digital Function Truth Table

Serial In/Serial Out

X

X

X

X

X

1

1

1

1

1

1

1

1

Reset all DACs

XX

X

X

X

X

0

11

1

0

11

1

1

1

1

No Operation

No Operation

D7

D6

D5

D4

D3

D2

D1

D0

MSB

LSB

0000

0

0

0

0

1111

1

1

1

0

1111

1

1

1

1

00

Table 2. DAC Transfer Function

Analog Output vs. Digital Code

00

0

0

0

1

CS0S CS1S CS2S CS3S

XX

X

X

1

Matched with 4 parallel

chip select data

CS0P to CS3P

XX

X

X

X

X

X

X

X

SDI

Data Input

X

X

X

X

X

X

X

X

X

X

X

SDO

Data Output

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

0

0

0

0

No Operation

Stop Shifting

Data In and

Out

XX

X

X

0

1

XX

X

X

Hi-Z

XX

X

No Operation