MP7651

12

Rev. 2.00

Figure 10. 8085 Interface (Simplified Diagram)

ALE

WR

SOD

8085

8

8

DATA BUS

+5 V

8212

A0 to A2

ADDRESS

DECODER

74LS138

E1

E3

E2

SDI

CLK

LD

RST

FROM SYSTEM RESET

8

ADDRESS BUS

NOTES:

1.

Clock generated by WR and decoding address 8000

2.

Data is clocked into the DAC shift register by executing memory write instructions. The clock input is

generated by decoding address 8000 and WR. Data is then loaded into the DAC register with a memory

write instruction to address 4000.

3.

Serial data must be present in the right justified format in registers H & L of the microprocessor.

CS0P to CS3P

3

MP7651

MP7651 EVALUATION BOARD

5 pF

Figure 1. Crosstalk Measurement Set-Up

1.6 Vp–p

1k

5k

20 pF

VR0

VR1

VR2

VR3

VR4

VR5

VR6

VR7

VO0

VO1

VO2

VO3

VO4

VO5

VO6

VO7

N/C

SDI

SDO

CLK

LD

RST

N/C

DGND

MP7651

DUT

All resistors = 50

Ω unless otherwise specified

Gain of all DACs set to 1 (no attenuation)

Test Load

Measurement

Buffer