PCF8545ATT datasheet(49/50 Pages) NXP

49 / 50 page

NXP Semiconductors

PCA8561

Automotive 18 × 4 LCD segment driver

Tables

Tab. 1.

Ordering Information ......................................... 2

Tab. 2.

Ordering options ................................................2

Tab. 3.

Pin description ...................................................5

Tab. 4.

Registers of the PCA8561 ................................ 6

Tab. 5.

Device_ctrl - device control command

Tab. 6.

Display_ctrl_1 - display control command 1

Tab. 7.

Display_ctrl_2 - display control command 2

Tab. 8.

Software_reset - software reset command

Tab. 9.

mapping ...........................................................11

Tab. 10. Selection of possible display configurations .... 13

Tab. 11. Biasing characteristics .....................................14

Tab. 12. I2C slave address byte ................................... 26

Tab. 13. R/W-bit description ..........................................26

Tab. 14. Serial interface ................................................ 26

Tab. 15. Address byte definition ....................................27

Tab. 16. Limiting values ................................................ 29

Tab. 17. Electrical characteristics ..................................30

Tab. 18. Frequency characteristics ............................... 33

Tab. 19. I2C-bus characteristics ....................................34

Tab. 20. SPI-bus characteristics ....................................35

Tab. 21. SnPb eutectic process (from J-STD-020D) ..... 40

Tab. 22. Lead-free process (from J-STD-020D) ............40

Tab. 23. Selection of LCD segment drivers ...................43

Tab. 24. Abbreviations ...................................................45

Tab. 25. Revision history ...............................................45

Figures

Fig. 1.

Block diagram of PCA8561A .............................3

Fig. 2.

Block diagram of PCA8561B .............................3

Fig. 3.

Pin configuration of PCA8561AHN

(HVQFN32) ........................................................4

Fig. 4.

Pin configuration of PCA8561BHN

(HVQFN32) ........................................................4

Fig. 5.

Address counter incrementing ...........................7

Fig. 6.

Reset pulse timing .......................................... 10

Fig. 7.

Display RAM organization bitmap for MUX

1:4 ................................................................... 12

Fig. 8.

Example of displays suitable for PCA8561 ......13

Fig. 9.

Typical system configuration using I2C-bus,

internal power-on reset disabled ..................... 13

Fig. 10.

Typical system configuration using SPI-

bus, internal power-on reset enabled .............. 14

Fig. 11.

Electro-optical characteristic: relative

transmission curve of the liquid .......................16

Fig. 12.

Static drive mode waveforms .......................... 17

Fig. 13.

Waveforms for the 1:2 multiplex drive mode

with 1⁄2 bias .................................................... 18

Fig. 14.

Waveforms for the 1:2 multiplex drive mode

with 1⁄3 bias .................................................... 19

Fig. 15.

Waveforms for the 1:3 multiplex drive mode

with 1⁄3 bias .................................................... 20

Fig. 16.

Waveforms for the 1:4 multiplex drive mode

with 1⁄3 bias .................................................... 21

Fig. 17.

Recommended power-up and power-off

sequence .........................................................23

Fig. 18.

I2C read and write protocol .............................23

Fig. 19.

I2C read and write signaling ........................... 24

Fig. 20.

Data transfer overview .................................... 26

Fig. 21.

SPI-bus write example: writing two data

bytes to registers 00h and 01h ........................27

Fig. 22.

SPI-bus read example: reading two data

bytes from registers 04h and 05h ....................28

Fig. 23.

Device protection diagram .............................. 28

Fig. 24.

Typical IDD and IDD(LCD) in power-down

mode as function of temperature .................... 31

Fig. 25.

Typical IDD(LCD) as function of display

load ..................................................................32

Fig. 26.

Typical IDD(LCD) as function of ffr ..................33

Fig. 27.

Relation of frame frequency (ffr), clock

frequency (fclk) and multiplex-rate (nMUX) ..... 34

Fig. 28.

I2C-bus timing waveforms ...............................35

Fig. 29.

SPI-bus timing waveforms .............................. 36

Fig. 30.

Package outline SOT617-3 (HVQFN32) of

PCA8561 ......................................................... 38

Fig. 31.

Temperature profiles for large and small

components .....................................................41

Fig. 32.

Footprint information for reflow soldering of

SOT617-3 (HVQFN32) of PCA8561 ............... 42

PCA8561

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 15 March 2021

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