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DA9220

High-Performance Dual-Channel DC-DC Converter

Datasheet

Revision 2.1

17-Sep-2020

CFR0011-120-00

29 of 62

Description

GPIO2_DEB[1:0]

GPIO2 input debounce time setting

GPIO2_DEB_RISE

GPIO2 input debounce rising edge enable

GPIO2_DEB_FALL

GPIO2 input debounce falling edge enable

4.2.3.4

OTP Reload (RELOAD)

Buck settings listed in Table 19 are reloaded from CONF registers by triggering GPIO configured as

RELOAD input.

The OTP reload happens at the same time for Buck1 and Buck2 settings. During reloading, Buck1/2

keep operating as configured without shut-down.

Table 19: OTP Reload Registers

Description

CH#_VSEL

CH# output voltage and operation selection.

0: A, 1: B

CH#_A_VOUT[7:0]

CH# output voltage setting A : CH#_A_VOUT * 10 mV

Setting under 0.3V is clamped to 0.3V, and setting over 1.9V is clamped to 1.9 V

CH#_B_VOUT[7:0]

CH# output voltage setting B : CH#_A_VOUT * 10 mV

Setting under 0.3 V is clamped to 0.3 V, and setting over 1.9V is clamped to 1.9 V

CH#_A_MODE[1:0]

Operation mode selection

0: Force PFM

1: Force PWM. full phase

2: Force PWM with phase shedding

3: Auto mode

CH#_B_MODE[1:0]

Operation mode selection

0: Force PFM

1: Force PWM. full phase

2: Force PWM with phase shedding

3: Auto mode

4.3

Operating Modes

4.3.1

DA9220 is ON when the IC_EN port is higher than VIH_EN and the supply voltage is higher than

VTHR_POR. Once enabled, the host processor can start communicating with DA9220 using the control

interface, after the tIC_EN delay.

4.3.2

OFF

DA9220 is OFF when the IC_EN port is lower than VIL_EN. In OFF, the bucks are always disabled and

LX nodes are pulled down by (typically 150 Ω) internal pull-down resistors.

4.4

I2C Communication

All features of DA9220 can be controlled with the I2C interface which is enabled or disabled in

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