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DA9220

High-Performance Dual-Channel DC-DC Converter

Datasheet

Revision 2.1

17-Sep-2020

CFR0011-120-00

19 of 62

4.1.3

Output Voltage Selection

The switching converter can be configured using the I2C interface.

For each buck converter two output voltages can be pre-configured in registers CH<x>_<A or

B>_VOUT. The output voltage can be selected by either toggling register bit CH<x>_VSEL or by re-

programming the selected voltage control register. Both changes will result in ramped voltage

transitions. After being enabled, the buck converter will, by default, use the register settings in

CH<x>_A_VOUT unless the output voltage selection is configured via the GPI port.

Registers CH<1 and 2>_VMAX limit the output voltage that can be set for each of the respective

buck converters.

Figure 14: Buck Output Voltage Control Concept

4.1.4

Soft Start-Up and Shutdown

To limit in-rush current from VSYS, the buck converters can perform a soft-start after being enabled.

The start-up behavior is a compromise between acceptable inrush current from the battery and turn-

on time. Individual ramp times can be configured for each buck converter in registers CH<1 and

2>_SR_STARTUP respectively. Rates higher than 20 mV/µs may produce overshoot during the

start-up phase, so they should be considered carefully.

A ramped power down can be selected in register bits CH<1 and 2>_SR_SHDN. When no ramp is

selected (immediate power down), the output node will be discharged only by the pull-down resistor,

if enabled in registers CH<1 and 2>_PD_DIS.

4.1.5

Current Limit

The integrated current limit protects the power stages and external coil from excessive current. The

buck current limit should be configured to at least 40 % higher than the required maximum output

current.

When the current limit is reached, each buck converter generates an event and an interrupt to the

host processor unless the interrupt has been masked using register M_OC<x> in SYS_MASK_1.

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