ICS1893AGLF datasheet(105/135 Pages) ICST

105 / 135 page

Chapter 9 Pin Diagram, Listings, and Descriptions

ICS1893AG, Rev. A 04/14/05

April, 2005

105

ICS1893AG Data Sheet - Preliminary

MDIO

Input/

Output

Management Data Input/Output.

The signal on this pin can be tri-stated and can be driven by one of the

following:

• A Station Management Entity (STA), to transfer command and data

information to the registers of the ICS1893AG.

• The ICS1893AG, to transfer status information.

All transfers and sampling are synchronous with the signal on the MDC

pin.

Note: If the ICS1893AG is to be used in an application that uses the

mechanical MII specification, MDIO must have a 1.5 k

Ω ±5%

pull-up resistor at the ICS1893AG end and a 2 k

Ω ±5% pull-down

resistor at the station management end. (These resistors enable

the station management to determine if the connection is intact.)

RXCLK

Output

Receive Clock.

The ICS1893AG sources the RXCLK to the MAC/repeater interface. The

ICS1893AG uses RXCLK to synchronize the signals on the following pins:

RXD[3:0], RXDV, and RXER. The following table contrasts the behavior

on the RXCLK pin when the mode for the ICS1893AG is either 10Base-T

or 100Base-TX.

Note: The signal on the RXCLK pin is conditioned by the RXTRI pin.

Table 9-8. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued)

Name

Number

Type

Pin Description

10Base-T

100Base-TX

The RXCLK frequency is 2.5

MHz.

The RXCLK frequency is 25 MHz.

The ICS1893AG generates its

RXCLK from the MDI data stream

using a digital PLL. When the MDI

data stream terminates, the PLL

continues to operate,

synchronously referenced to the

last packet received.

The ICS1893AG generates its

RXCLK from the MDI data stream

while there is a valid link (that is,

either data or IDLEs). In the

absence of a link, the ICS1893AG

uses the REF_IN clock to

generate the RXCLK.

The ICS1893AG switches

between clock sources during the

period between when its CRS is

asserted and prior to its RXDV

being asserted. While the

ICS1893AG is locking onto the

incoming data stream, a clock

phase change of up to 360

degrees can occur.

While the ICS1893AG is bringing

up a link, a clock phase change of

up to 360 degrees can occur.

The RXCLK aligns once per

packet.

The RXCLK aligns once, when

the link is being established.

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