ICS1893AGLF datasheet(7/135 Pages) ICST

7 / 135 page

Table of Contents

ICS1893AG, Rev. A 04/14/05

April, 2005

ICS1893AG Data Sheet - Preliminary

Table of Contents

Section

Title

Page

8.14

8.14.1

Node/Repeater Configuration (bit 19.15) ...............................................................97

8.14.2

Hardware/Software Priority Status (bit 19.14) ........................................................97

8.14.3

Remote Fault (bit 19.13) ........................................................................................97

8.14.4

ICS Reserved (bits 19.12:8) ...................................................................................97

8.14.5

Twisted Pair Tri-State Enable, TPTRI (bit 19.7) .....................................................97

8.14.6

ICS Reserved (bits 19.6:1) .....................................................................................97

8.14.7

Automatic 100Base-TX Power-Down (bit 19.0) .....................................................97

Chapter 9

Pin Diagram, Listings, and Descriptions ....................................................................... 98

9.1

ICS1893AG Pin Diagram .......................................................................................98

9.2

ICS1893AG Pin Descriptions .................................................................................99

9.2.1

Transformer Interface Pins ...................................................................................100

9.2.2

Multi-Function (Multiplexed) Pins: PHY Address and LED Pins ...........................101

9.2.3

Configuration Pins.................................................................................................104

9.2.4

MAC Interface Pins ...............................................................................................105

9.2.5

Ground and Power Pins........................................................................................109

Chapter 10

DC and AC Operating Conditions............................................................................... 110

10.1

Absolute Maximum Ratings .................................................................................110

10.2

Recommended Operating Conditions ..................................................................110

10.3

Recommended Component Values .....................................................................111

10.4

DC Operating Characteristics ..............................................................................112

10.4.1

DC Operating Characteristics for Supply Current ................................................112

10.4.2

DC Operating Characteristics for TTL Inputs and Outputs ..................................112

10.4.3

DC Operating Characteristics for REF_IN ...........................................................113

10.4.4

DC Operating Characteristics for Media Independent Interface ..........................113

10.5

Timing Diagrams ..................................................................................................114

10.5.1

Timing for Clock Reference In (REF_IN) Pin .......................................................114

10.5.2

Timing for Transmit Clock (TXCLK) Pins .............................................................115

10.5.3

Timing for Receive Clock (RXCLK) Pins ..............................................................116

10.5.4

100M MII: Synchronous Transmit Timing .............................................................117

10.5.5

10M MII: Synchronous Transmit Timing ..............................................................118

10.5.6

100M/MII Media Independent Interface: Synchronous Receive Timing ...............119

10.5.7

MII Management Interface Timing .......................................................................120

10.5.8

10M Media Independent Interface: Receive Latency ...........................................121

10.5.9

10M Media Independent Interface: Transmit Latency...........................................122

10.5.10

100M/MII Media Independent Interface: Transmit Latency...................................123

10.5.11

100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)................124

10.5.12

10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)..................125

10.5.13

100M MII Media Independent Interface: Receive Latency....................................126

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