ICS1893AGLF datasheet(56/135 Pages) ICST

56 / 135 page

ICS1893AG, Rev A 04/14/05

April, 2005

Chapter 8 Management Register Set

ICS1893AG Data Sheet - Preliminary

8.1.2 Management Register Bit Access

The ICS1893AG Management Registers include one or more of the following types of bits:

8.1.3 Management Register Bit Default Values

The tables in this chapter specify for each register bit the default value, if one exists. The ICS1893AG sets

all Management Register bits to their default values after a reset. Table 8-4 lists the valid default values for

ICS1893AG Management Register bits.

Note: The ICS1893AG has a number of reserved bits throughout the Management Registers. Most of

these bits provide enhanced test modes. The Management Register tables provide the default

values for these bits. The STA must not change the value of these bits under any circumstance. If

the STA inadvertently changes the default values of these reserved register bits, normal operation

of the ICS1893AG can be affected.

Table 8-3. Description of Management Register Bit Types

Management

Bit

Symbol

Description

Read-Only

An STA can obtain the value of a RO register bit. However, it cannot

alter the value of (that is, it cannot write to) an RO register bit. The

ICS1893AG isolates any STA attempt to write a value to an RO bit.

Command Override

Write

An STA can read a value from a CW register bit. However, write

operations are conditional, based on the value of the Command

• Zero (the default), the ICS1893AG isolates STA attempts to write

to the CW bits (that is, CW bits cannot be altered when bit 16.15 is

logic zero).

• One, the ICS1893AG permits an STA to alter the value of the CW

bits in the subsequent register write. (Bit 16.15 is self-clearing and

automatically clears to zero on the subsequent write.)

Read/Write

R/W

An STA can unconditionally read from or write to a R/W register bit.

Read/Write Zero

R/W0

An STA can unconditionally read from a R/W0 register bit, but only a

‘0’ value can be written to this bit.

Table 8-4. Range of Possible Valid Default Values for ICS1893AG Register Bits

Default Condition

Default Value

–

Indicates there is no default value for the bit

Indicates the bit’s default value is logic zero

Indicates the bit’s default value is logic one

State of pin at reset

For some bits, the default value depends on the state (that is, the logic value) of a

particular pin at reset (that is, the logic value of a pin is latched at reset). An

example of pins that have a default condition that depends on the state of the pin

at reset are the PHY / LED pins (P0AC, P1CL, P2LI, P3TD, and P4RD) discussed

in the following sections:

• Section 6.5, “Status Interface”

• Section 8.11, “Register 16: Extended Control Register”

• Section 9.2.2, “Multi-Function (Multiplexed) Pins: PHY Address and LED Pins”

ICS1893AGLF датащи(PDF) 56 Page - Integrated Circuit Systems

ICS1893AGLF датащи(HTML) 56 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL