MPC7445 datasheet(16/56 Pages) NXP

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MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

Electrical and Thermal Characteristics

5.2.2

Processor Bus AC Specifications

Table 9 provides the processor bus AC timing specifications for the MPC7447A as defined in Figure 4 and

Figure 5.

Table 9. Processor Bus AC Timing Specifications1

At recommended operating conditions. See Table 4.

Parameter

Symbol 2

All Speed Grades

Unit

Notes

Min

Max

Input setup times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL,

PMON_IN, SHD[0:1]

BMODE[0:1], BVSEL

tAVKH

tDVKH

tIVKH

tMVKH

1.8

—

Input hold times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL,

PMON_IN, SHD[0:1]

BMODE[0:1], BVSEL

tAXKH

tDXKH

tIXKH

tMXKH

—

Output valid times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT,

PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3], WT

ARTRY, SHD[0:1]

tKHAV

tKHDV

tKHOV

tKHTSV

tKHARV

—

2.0

Output hold times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT,

PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3], WT

ARTRY, SHD[0:1]

tKHAX

tKHDX

tKHOX

tKHTSX

tKHARX

0.5

—

SYSCLK to output enable

tKHOE

0.5

—

SYSCLK to output high impedance (all except TS, ARTRY,

SHD0, SHD1)

tKHOZ

—3.5

SYSCLK to TS high impedance after precharge

tKHTSPZ

—1

tSYSCLK

3, 4, 5

Maximum delay to ARTRY/SHD0/SHD1 precharge

tKHARP

—1

tSYSCLK 3, 5, 6, 7

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