PCF8553DTTSLASHA datasheet(27/51 Pages) NXP

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NXP Semiconductors

PCF8553

40 × 4 LCD segment driver

Slave address

Bit

MSB

LSB

R/W

Table 12. I2C slave address byte

The least significant bit of the slave address byte is bit R/W (see Table 13).

R/W

Description

write data

read data

Table 13. R/W-bit description

Bit 1 and bit 2 of the slave address are defined by connecting the input pins A0 and A1

to either VSS (logic 0) or VDD (logic 1). Therefore, four instances of PCF8553 can be

distinguished on the same I2C-bus.

10.2 SPI-bus interface

Data transfer to the device is made via a 3-line SPI-bus (see Table 14). There is no

dedicated output data line. The SPI-bus is initialized whenever the chip enable line pin

CE is pulled down.

Symbol Function

Description

chip enable input[1]; active LOW when HIGH, the interface is reset

SCL

serial clock input

input may be higher than VDD

SDIO

serial data input/output

input data are sampled on the rising edge of SCL,

output data are valid after the falling edge of SCL

Table 14. Serial interface

[1]

The chip enable must not be wired permanently LOW.

10.2.1 Data transmission

The chip enable signal is used to identify the transmitted data. Each data transfer is a

byte with the Most Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable signal CE. The first byte

transmitted is the register address comprising of the address pointer and the R/W bit.

aaa-011938

data bus

DATA

Figure 18. Data transfer overview

PCF8553

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 April 2021

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