AT25SF641 datasheet(21/76 Pages) DIALOG

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AT25SF641

DS-25SF641–111E–3/2018

The instruction is entered by driving CS low and sending the instruction code “05h” for Status Register-1 or “35h” for Status

Register-2 into the SI pin on the rising edge of SCK. The status register bits are then shifted out on the SO pin at the falling

edge of SCK with most significant bit (MSB) first as shown in (Figure 7-4 and Figure 7-5). The Status Register can be read

continuously. The instruction is completed by driving CS high.

Figure 7-4.

Read Status Register Instruction (SPI Mode)

Figure 7-5.

Read Status Register Instruction (QPI Mode)

7.6

Write Status Register (01h)

The Write Status Register instruction is to write only non-volatile Status Register-1 bits (SRP0, SEC, TB, BP2, BP1

and BP0) and Status Register-2 bits (CMP, QE and SRP1). All other Status Register bit locations are read-only and will

not be affected by the Write Status Register instruction.

A Write Enable instruction must previously have been issued prior to setting Write Status Register Instruction (Status

instruction code, and then writing the status register data byte as illustrated in Figure 7-6 and Figure 7-7.

The CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write

Status Register instruction will not be executed. If CS is driven high after the eighth clock, the CMP QE and SRP1 bits

will be cleared to 0. After CS is driven high, the self- timed Write Status Register cycle will commence for a time duration

of t

W (See Section 8.7, AC Electrical Characteristics).

While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to

check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the

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