AT25SF641 datasheet(52/76 Pages) DIALOG

номер детали	AT25SF641

подробное описание детали	64-Mbit, 2.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

PDF	76 Pages

Scroll/Zoom	100%

производитель	DIALOG [Dialog Semiconductor]

домашняя страница	http://www.dialog-semiconductor.com/

Logo

52 / 76 page

AT25SF641

DS-25SF641–111E–3/2018

Figure 7-55. Set Read Parameters instruction (QPI Mode)

7.34

Enable Reset (66h) and Reset (99h)

Because of the small package and the limitation on the number of pins, the AT25SF641 provide a software Reset

instruction instead of a dedicated RESET pin.

Once the Reset instruction is accepted, any on-going internal operations will be terminated and the device will return to

its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable

Latch (WEL) status, Program/Erase Suspend status, Continuous Read Mode bit setting, Read parameter setting and

Wrap bit setting.

“Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI mode. To avoid accidental

reset, both instructions must be issued in sequence. Any other instructions other than “Reset (99h)” after the “Enable

(66h)” instruction disables the “Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is

needed to reset the device. Once the Reset instruction is accepted by the device takes approximately t

RST = 30us to

reset. During this period, no instruction will be accepted.

Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset

instruction sequence is accepted by device. It is recommended to check the BUSY bit and the SUS bit in Status Register

before issuing the Reset instruction sequence.

Figure 7-56. Enable Reset and Reset Instruction (SPI Mode)

AT25SF641 датащи(PDF) 52 Page - Dialog Semiconductor