14

AT25DF256

DS-25DF256–035D–2/2017

command to change the value of the Block Protection (BP0) bit in the Status Register. The following table outlines the

two states of the BP0 bit and the associated protection area.

When the BP0 bit of the Status Register is in the logical “1” state, the entire memory array will be protected against

program or erase operations. Any attempts to send a Byte/Page Program command, a Block Erase command, or a Chip

Erase command will be ignored by the device.

As a safeguard against accidental or erroneous protecting or unprotecting of the memory array, the BP0 bit itself can be

locked from updates by using the WP pin and the BPL (Block Protection Locked) bit of the Status Register (see

“Protected States and the Write Protect Pin” on page 14 for more details).

The BP0 bit of the Status Register is a nonvolatile bit; therefore, the BP0 bit will retain its state even after the device has

been power cycled. Care should be taken to ensure that BP0 is in the logical “1” state before powering down for those

applications that wish to have the memory array fully protected upon power up. The default state for BP0 when shipped

from Adesto is “0”.

9.4

Protected States and the Write Protect Pin

The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array.

Instead, the WP pin, in conjunction with the BPL (Block Protection Locked) bit in the Status Register, is used to control

the hardware locking mechanism of the device. For hardware locking to be active, two conditions must be met-the WP

pin must be asserted and the BPL bit must be in the logical “1” state.

When hardware locking is active, the Block Protection (BP0) bit is locked and the BPL bit itself is also locked. Therefore,

if the memory array is protected, it will be locked in the protected state, and if the memory array is unprotected, it will be

locked in the unprotected state. These states cannot be changed as long as hardware locking is active, so the Write

Status Register command will be ignored. In order to modify the protection status of the memory array, the WP pin must

first be deasserted, and the BPL bit in the Status Register must be reset back to the logical “0” state using the Write

Status Register command.

If the WP pin is permanently connected to GND, then once the BPL bit is set to a logical “1”, the only way to reset the bit

back to the logical “0” state is to power-cycle the device. This allows a system to power-up with all sectors software

protected but not hardware locked. Therefore, sectors can be unprotected and protected as needed and then hardware

locked at a later time by simply setting the BPL bit in the Status Register.

be set to a logical “1”, but doing so will not lock the BP0 bit.

Table 9-2 details the various protection and locking states of the device.

Table 9-1.

Memory Array Protection

Protection Level

BP0

Protected Memory Address

None

0

None

Full Memory

1

00000h - 007FFFh