5

AT25DF256

DS-25DF256–035D–2/2017

4.

Memory Array

To provide the greatest flexibility, the memory array of the AT25DF256 can be erased in three levels of granularity

including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing

both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the

breakdown of each erase level.

Figure 4-1. Memory Architecture Diagram

5.

Device Operation

The AT25DF256 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI

Master. The SPI Master communicates with the AT25DF256 via the SPI bus which is comprised of four signal lines: Chip

Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).

The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the

SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DF256

supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the

polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any

data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge

of SCK.

Figure 5-1. SPI Mode 0 and 3

5.1

Dual Output Read

The ATx features a Dual-Output Read mode that allow two bits of data to be clocked out of the device every clock cycle

to improve throughput. To accomplish this, both the SI and SO pins are utilized as outputs for the transfer of data bytes.

With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.

32KB

4KB

1-256 Byte

Block Erase

Block Erase

Page Program

(52h Command)

(20h Command)

(02h Command)

4KB

007FFFh – 007000h

256 Bytes

007FFFh – 007F00h

4KB

006FFFh – 006000h

256 Bytes

007EFFh – 007E00h

4KB

005FFFh – 005000h

256 Bytes

007DFFh – 007D00h

4KB

4KB

4KB

002FFFh – 002000h

256 Bytes

0002FFh – 000200h

4KB

001FFFh – 001000h

256 Bytes

0001FFh – 000100h

4KB

000FFFh – 000000h

256 Bytes

0000FFh – 000000h

004FFFh – 004000h

003FFFh – 003000h

Block Erase Detail

Page Program Detail

Page Address

Block Address

Range

Range

32KB

SCK

CS

SI

SO

MSB

LSB

MSB

LSB